TY - GEN
T1 - A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR
AU - Shu, Guanghua
AU - Saxena, Saurabh
AU - Choi, Woo Seok
AU - Talegaonkar, Mrumnay
AU - Inti, Rajesh
AU - Elshazly, Amr
AU - Young, Brian
AU - Hanumolu, Pavan Kumar
PY - 2013
Y1 - 2013
N2 - A reference-less half-rate digital CDR implements proportional control in phase domain with a phase-rotating PLL (PRPLL) which decouples jitter transfer (JTRAN) bandwidth and jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on phase detector gain. Fabricated in a 90nm CMOS process, the prototype CDR achieves 2MHz JTRAN, 16MHz JTOL, and consumes 13.1mW from 1V supply at 5Gb/s with BER<10-12.
AB - A reference-less half-rate digital CDR implements proportional control in phase domain with a phase-rotating PLL (PRPLL) which decouples jitter transfer (JTRAN) bandwidth and jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on phase detector gain. Fabricated in a 90nm CMOS process, the prototype CDR achieves 2MHz JTRAN, 16MHz JTOL, and consumes 13.1mW from 1V supply at 5Gb/s with BER<10-12.
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M3 - Conference contribution
AN - SCOPUS:84883750720
SN - 9784863483484
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - C278-C279
BT - 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
T2 - 2013 Symposium on VLSI Circuits, VLSIC 2013
Y2 - 12 June 2013 through 14 June 2013
ER -