A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR

Guanghua Shu, Saurabh Saxena, Woo Seok Choi, Mrumnay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A reference-less half-rate digital CDR implements proportional control in phase domain with a phase-rotating PLL (PRPLL) which decouples jitter transfer (JTRAN) bandwidth and jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on phase detector gain. Fabricated in a 90nm CMOS process, the prototype CDR achieves 2MHz JTRAN, 16MHz JTOL, and consumes 13.1mW from 1V supply at 5Gb/s with BER<10-12.

Original languageEnglish (US)
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
PagesC278-C279
StatePublished - Sep 17 2013
Externally publishedYes
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: Jun 12 2013Jun 14 2013

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period6/12/136/14/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Shu, G., Saxena, S., Choi, W. S., Talegaonkar, M., Inti, R., Elshazly, A., Young, B., & Hanumolu, P. K. (2013). A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers (pp. C278-C279). [6578694] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).