A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS

Karthikeyan Reddy, Siladitya Dey, Sachin Rao, Brian Young, Praveen Prabha, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A wide bandwidth VCO-based continuous-time ΔΣ modulator that uses combined phase and frequency feedback to mitigate VCO non-linearity and ease DEM timing requirement is presented. Fabricated in 65nm CMOS process, the prototype modulator operates at 1.2GS/s and achieves 71.5dB SNDR in 50MHz bandwidth while consuming 54mW of power, which translates to an FoM of 176fJ/conv-step.

Original languageEnglish (US)
Title of host publication2015 Symposium on VLSI Circuits, VLSI Circuits 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC256-C257
ISBN (Electronic)9784863485020
DOIs
StatePublished - Aug 31 2015
Event29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan
Duration: Jun 17 2015Jun 19 2015

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2015-August

Other

Other29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
CountryJapan
CityKyoto
Period6/17/156/19/15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Reddy, K., Dey, S., Rao, S., Young, B., Prabha, P., & Hanumolu, P. K. (2015). A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015 (pp. C256-C257). [7231278] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231278