A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS

Karthikeyan Reddy; Siladitya Dey; Sachin Rao; Brian Young; Praveen Prabha; Pavan Kumar Hanumolu

doi:10.1109/VLSIC.2015.7231278

A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS

Karthikeyan Reddy, Siladitya Dey, Sachin Rao, Brian Young, Praveen Prabha, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A wide bandwidth VCO-based continuous-time ΔΣ modulator that uses combined phase and frequency feedback to mitigate VCO non-linearity and ease DEM timing requirement is presented. Fabricated in 65nm CMOS process, the prototype modulator operates at 1.2GS/s and achieves 71.5dB SNDR in 50MHz bandwidth while consuming 54mW of power, which translates to an FoM of 176fJ/conv-step.

Original language	English (US)
Title of host publication	2015 Symposium on VLSI Circuits, VLSI Circuits 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C256-C257
ISBN (Electronic)	9784863485020
DOIs	https://doi.org/10.1109/VLSIC.2015.7231278
State	Published - Aug 31 2015
Event	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan Duration: Jun 17 2015 → Jun 19 2015

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2015-August

Other

Other	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
Country/Territory	Japan
City	Kyoto
Period	6/17/15 → 6/19/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Online availability

10.1109/VLSIC.2015.7231278

Library availability

Discover UIUC Full Text

Cite this

Reddy, K., Dey, S., Rao, S., Young, B., Prabha, P., & Hanumolu, P. K. (2015). A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015 (pp. C256-C257). [7231278] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231278

A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. / Reddy, Karthikeyan; Dey, Siladitya; Rao, Sachin et al.
2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. C256-C257 7231278 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Reddy, K, Dey, S, Rao, S, Young, B, Prabha, P & Hanumolu, PK 2015, A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. in 2015 Symposium on VLSI Circuits, VLSI Circuits 2015., 7231278, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. C256-C257, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, Kyoto, Japan, 6/17/15. https://doi.org/10.1109/VLSIC.2015.7231278

Reddy K, Dey S, Rao S, Young B, Prabha P, Hanumolu PK. A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. C256-C257. 7231278. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2015.7231278

@inproceedings{8b9322b8cde94de8bc334a52e552e92f,

title = "A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS",

abstract = "A wide bandwidth VCO-based continuous-time ΔΣ modulator that uses combined phase and frequency feedback to mitigate VCO non-linearity and ease DEM timing requirement is presented. Fabricated in 65nm CMOS process, the prototype modulator operates at 1.2GS/s and achieves 71.5dB SNDR in 50MHz bandwidth while consuming 54mW of power, which translates to an FoM of 176fJ/conv-step.",

author = "Karthikeyan Reddy and Siladitya Dey and Sachin Rao and Brian Young and Praveen Prabha and Hanumolu, {Pavan Kumar}",

note = "Publisher Copyright: {\textcopyright} 2015 JSAP.; 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 ; Conference date: 17-06-2015 Through 19-06-2015",

year = "2015",

month = aug,

day = "31",

doi = "10.1109/VLSIC.2015.7231278",

language = "English (US)",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "C256--C257",

booktitle = "2015 Symposium on VLSI Circuits, VLSI Circuits 2015",

address = "United States",

}

TY - GEN

T1 - A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS

AU - Reddy, Karthikeyan

AU - Dey, Siladitya

AU - Rao, Sachin

AU - Young, Brian

AU - Prabha, Praveen

AU - Hanumolu, Pavan Kumar

PY - 2015/8/31

Y1 - 2015/8/31

N2 - A wide bandwidth VCO-based continuous-time ΔΣ modulator that uses combined phase and frequency feedback to mitigate VCO non-linearity and ease DEM timing requirement is presented. Fabricated in 65nm CMOS process, the prototype modulator operates at 1.2GS/s and achieves 71.5dB SNDR in 50MHz bandwidth while consuming 54mW of power, which translates to an FoM of 176fJ/conv-step.

AB - A wide bandwidth VCO-based continuous-time ΔΣ modulator that uses combined phase and frequency feedback to mitigate VCO non-linearity and ease DEM timing requirement is presented. Fabricated in 65nm CMOS process, the prototype modulator operates at 1.2GS/s and achieves 71.5dB SNDR in 50MHz bandwidth while consuming 54mW of power, which translates to an FoM of 176fJ/conv-step.

UR - http://www.scopus.com/inward/record.url?scp=84957894305&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84957894305&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2015.7231278

DO - 10.1109/VLSIC.2015.7231278

M3 - Conference contribution

AN - SCOPUS:84957894305

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - C256-C257

BT - 2015 Symposium on VLSI Circuits, VLSI Circuits 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015

Y2 - 17 June 2015 through 19 June 2015

ER -

A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS

Abstract

Publication series

Other

ASJC Scopus subject areas

Online availability

Library availability

Related links

Fingerprint

Cite this