A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop

Mohamed Badr Younis; Mostafa Ahmed; Tianyu Wang; Ahmed Abdelrahman; Mahmoud Khalil; Anup Jose; Pavan Kumar Hanumolu

doi:10.23919/VLSITechnologyandCir57934.2023.10185437

A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop

Mohamed Badr Younis, Mostafa Ahmed, Tianyu Wang, Ahmed Abdelrahman, Mahmoud Khalil, Anup Jose, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 5.2 Gb/s contactless transceiver using dual-edge tracking clock and data recovery loop (DE-CDR) for giant video walls is presented. Fabricated in a 65nm CMOS process and using a 1 V power supply, the transceiver communicates error-freely (BER<10-12) for up to 3 mm air-gap distance using capacitive-coupling and achieves an energy efficiency of 4.7 pJ/bit with a 10 MHz JTOL corner frequency.

Original language	English (US)
Title of host publication	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863488069
DOIs	https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185437
State	Published - 2023
Event	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan Duration: Jun 11 2023 → Jun 16 2023

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2023-June
ISSN (Print)	0743-1562

Conference

Conference	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/Territory	Japan
City	Kyoto
Period	6/11/23 → 6/16/23

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.23919/VLSITechnologyandCir57934.2023.10185437

Library availability

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Younis, M. B., Ahmed, M., Wang, T., Abdelrahman, A., Khalil, M., Jose, A., & Hanumolu, P. K. (2023). A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185437

A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. / Younis, Mohamed Badr; Ahmed, Mostafa; Wang, Tianyu et al.
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2023-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Younis, MB, Ahmed, M, Wang, T, Abdelrahman, A, Khalil, M, Jose, A & Hanumolu, PK 2023, A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. in 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2023-June, Institute of Electrical and Electronics Engineers Inc., 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Kyoto, Japan, 6/11/23. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185437

Younis MB, Ahmed M, Wang T, Abdelrahman A, Khalil M, Jose A et al. A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSITechnologyandCir57934.2023.10185437

Younis, Mohamed Badr ; Ahmed, Mostafa ; Wang, Tianyu et al. / A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology).

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abstract = "A 5.2 Gb/s contactless transceiver using dual-edge tracking clock and data recovery loop (DE-CDR) for giant video walls is presented. Fabricated in a 65nm CMOS process and using a 1 V power supply, the transceiver communicates error-freely (BER<10-12) for up to 3 mm air-gap distance using capacitive-coupling and achieves an energy efficiency of 4.7 pJ/bit with a 10 MHz JTOL corner frequency.",

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A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop

Abstract

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