TY - JOUR
T1 - A 5 Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis
AU - Saxena, Saurabh
AU - Nandwana, Romesh Kumar
AU - Hanumolu, Pavan Kumar
N1 - Copyright:
Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2014/8
Y1 - 2014/8
N2 - In this paper, we present a time-based equalization scheme to implement transmit de-emphasis in voltage-mode drivers. Using two-level pulse-width modulation, this work decouples the tradeoff between impedance matching, output swing, and de-emphasis resolution in conventional voltage-mode drivers using voltage-based de-emphasis. A prototype PWM-based 5 Gb/s voltage-mode transmitter was implemented in a 90 nm CMOS process and characterized across different channels and output swings. The horizontal/vertical eye opening (BER=10 -12) at the end of 60 and 96 in stripline channels is 78 mv/0.6 UI and 8 mV/0.3 UI, respectively. Duty cycle distortion of the clock severely reduced the margins, so the overall performance can be improved by applying duty-cycle correction to clock signals. The transmitter consumes a total power 15.6 mW of which 2.5 mW is consumed in the digital PLL and 7.8 mW in the pre-/output drivers and regulators. This translates to a power efficiency of 3.1 mW/Gb/s, which compares favorably with the state of the art.
AB - In this paper, we present a time-based equalization scheme to implement transmit de-emphasis in voltage-mode drivers. Using two-level pulse-width modulation, this work decouples the tradeoff between impedance matching, output swing, and de-emphasis resolution in conventional voltage-mode drivers using voltage-based de-emphasis. A prototype PWM-based 5 Gb/s voltage-mode transmitter was implemented in a 90 nm CMOS process and characterized across different channels and output swings. The horizontal/vertical eye opening (BER=10 -12) at the end of 60 and 96 in stripline channels is 78 mv/0.6 UI and 8 mV/0.3 UI, respectively. Duty cycle distortion of the clock severely reduced the margins, so the overall performance can be improved by applying duty-cycle correction to clock signals. The transmitter consumes a total power 15.6 mW of which 2.5 mW is consumed in the digital PLL and 7.8 mW in the pre-/output drivers and regulators. This translates to a power efficiency of 3.1 mW/Gb/s, which compares favorably with the state of the art.
KW - Digital phase-locked loop (DPLL)
KW - PWM equalization,voltage-mode TX
KW - wireline
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U2 - 10.1109/JSSC.2014.2317142
DO - 10.1109/JSSC.2014.2317142
M3 - Article
AN - SCOPUS:84905407003
VL - 49
SP - 1827
EP - 1836
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 8
M1 - 6809856
ER -