A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9ps_rms integrated-jitter

Keyphrases

• Ring-like Structures 100%
• Wide Bandwidth 100%
• Integrated Jitter 100%
• Fractional-N 100%
• Wide Frequency Range 50%
• Ring Oscillator 50%
• Filter Architecture 50%
• Jitter 50%
• Oscillator Basis 50%
• Digital Loop Filter 50%
• Low Jitter 50%
• 65nm CMOS 50%
• In-band Phase Noise 50%
• Noise Cancellation Technique 50%
• Quantization Noise 50%
• Dual-path 50%

Engineering

• Phase Noise 100%
• Loop Filter 100%
• Noise Cancellation 100%
• Phase Locked Loop 100%
• Quantization Noise 100%