@inproceedings{00a61b446ba7478aa02bedb243fdbf3f,
title = "A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter",
abstract = "In this paper, a ring oscillator based fractional-N DPLL that achieves low jitter by extending bandwidth using noise cancellation techniques is presented. A dual-path digital loop filter architecture is employed to resolve the ΔΣ DAC quantization noise challenge. Fabricated in 65nm CMOS process, the proposed PLL operates over a wide frequency range of 4GHz-5.5GHz and achieves 1.9psrms jitter while consuming only 4mW. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNDPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference. The FoM is -228.5dB, which is at least 20dB better than all reported ring-based FNDPLLs.",
keywords = "DCO, DPLL, DTC, Fractional-N, TDC, fractional divider, jitter, ring VCO, time amplifier",
author = "Ahmed Elkholy and Saurabh Saxena and Nandwana, {Romesh Kumar} and Amr Elshazly and Hanumolu, {Pavan Kumar}",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE Custom Integrated Circuits Conference, CICC 2015 ; Conference date: 28-09-2015 Through 30-09-2015",
year = "2015",
month = nov,
day = "25",
doi = "10.1109/CICC.2015.7338376",
language = "English (US)",
series = "Proceedings of the Custom Integrated Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 IEEE Custom Integrated Circuits Conference, CICC 2015",
address = "United States",
}