A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter

M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. Choi, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A phase interpolator (PI) based fractional divider is used to improve the quantization noise shaping properties of a 1-bit ΔΣ frequency-to-digital converter (FDC). Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed FDC in place of a high resolution TDC and achieves-102dBc/Hz in-band phase noise and 852fsrms integrated jitter (1k-40M) while generating 5.054GHz output from 31.25MHz input.

Original languageEnglish (US)
Title of host publication2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479933273
DOIs
StatePublished - Jan 1 2014
Event28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States
Duration: Jun 10 2014Jun 13 2014

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other28th IEEE Symposium on VLSI Circuits, VLSIC 2014
CountryUnited States
CityHonolulu, HI
Period6/10/146/13/14

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Talegaonkar, M., Anand, T., Elkholy, A., Elshazly, A., Nandwana, R. K., Saxena, S., Young, B., Choi, W., & Hanumolu, P. K. (2014). A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers [6858392] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2014.6858392