A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training

Sujan Kumar Gonugondla, Mingu Kang, Naresh Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Embedded sensory systems (Fig. 31.2.1) continuously acquire and process data for inference and decision-making purposes under stringent energy constraints. These always-ON systems need to track changing data statistics and environmental conditions, such as temperature, with minimal energy consumption. Digital inference architectures [1,2] are not well-suited for such energy-constrained sensory systems due to their high energy consumption, which is dominated (>75%) by the energy cost of memory read accesses and digital computations. In-memory architectures [3,4] significantly reduce the energy cost by embedding pitch-matched analog computations in the periphery of the SRAM bitcell array (BCA). However, their analog nature combined with stringent area constraints makes these architectures susceptible to process, voltage, and temperature (PVT) variation. Previously, off-chip training [4] has been shown to be effective in compensating for PVT variations of in-memory architectures. However, PVT variations are die-specific and data statistics in always-ON sensory systems can change over time. Thus, on-chip training is critical to address both sources of variation and to enable the design of energy efficient always-ON sensory systems based on in-memory architectures. The stochastic gradient descent (SGD) algorithm is widely used to train machine learning algorithms such as support vector machines (SVMs), deep neural networks (DNNs) and others. This paper demonstrates the use of on-chip SGD-based training to compensate for PVT and data statistics variation to design a robust in-memory SVM classifier.

Original languageEnglish (US)
Title of host publication2018 IEEE International Solid-State Circuits Conference, ISSCC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages490-492
Number of pages3
ISBN (Electronic)9781509049394
DOIs
StatePublished - Mar 8 2018
Event65th IEEE International Solid-State Circuits Conference, ISSCC 2018 - San Francisco, United States
Duration: Feb 11 2018Feb 15 2018

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume61
ISSN (Print)0193-6530

Other

Other65th IEEE International Solid-State Circuits Conference, ISSCC 2018
CountryUnited States
CitySan Francisco
Period2/11/182/15/18

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Gonugondla, S. K., Kang, M., & Shanbhag, N. (2018). A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018 (pp. 490-492). (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 61). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2018.8310398