A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM building block in 65nm CMOS

Muhammad Khellah, Nam Sung Kim, Jason Howard, Greg Ruhl, Murad Sunna, Yibin Ye, James Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An SRAM macro, implemented in a 65nm CMOS process, uses a dual supply to maximize density while enabling the use of low voltage for the processor core. Measurements of a 256kb block show 4.2GHz operation using 29mW from 1.2V at 85°C, with core logic operating down to 0.7V and a sleep biasing scheme that autonomously compensates for PVT and aging.

Original languageEnglish (US)
Title of host publication2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
StatePublished - 2006
Externally publishedYes
Event2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: Feb 6 2006Feb 9 2006

Other

Other2006 IEEE International Solid-State Circuits Conference, ISSCC
Country/TerritoryUnited States
CitySan Francisco, CA
Period2/6/062/9/06

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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