A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement

Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A calibration-free ring oscillator based fractional-N clock multiplier using hybrid phase/current-mode phase interpolator is presented. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25GHz-to-4.75GHz with in-band noise floor of-104dBc/Hz and 1.5ps integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of-225.8dB.

Original languageEnglish (US)
Title of host publication2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479933273
DOIs
StatePublished - Jan 1 2014
Event28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States
Duration: Jun 10 2014Jun 13 2014

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other28th IEEE Symposium on VLSI Circuits, VLSIC 2014
CountryUnited States
CityHonolulu, HI
Period6/10/146/13/14

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Nandwana, R. K., Anand, T., Saxena, S., Kim, S. J., Talegaonkar, M., Elkholy, A., Choi, W. S., Elshazly, A., & Hanumolu, P. K. (2014). A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers [6858446] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2014.6858446