A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement

Romesh Kumar Nandwana; Tejasvi Anand; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Ahmed Elkholy; Woo Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu

doi:10.1109/VLSIC.2014.6858446

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement

Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A calibration-free ring oscillator based fractional-N clock multiplier using hybrid phase/current-mode phase interpolator is presented. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25GHz-to-4.75GHz with in-band noise floor of-104dBc/Hz and 1.5ps integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of-225.8dB.

Original language	English (US)
Title of host publication	2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781479933273
DOIs	https://doi.org/10.1109/VLSIC.2014.6858446
State	Published - 2014
Event	28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States Duration: Jun 10 2014 → Jun 13 2014

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	28th IEEE Symposium on VLSI Circuits, VLSIC 2014
Country/Territory	United States
City	Honolulu, HI
Period	6/10/14 → 6/13/14

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Online availability

10.1109/VLSIC.2014.6858446

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Nandwana, R. K., Anand, T., Saxena, S., Kim, S. J., Talegaonkar, M., Elkholy, A., Choi, W. S., Elshazly, A., & Hanumolu, P. K. (2014). A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers [6858446] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2014.6858446

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. / Nandwana, Romesh Kumar; Anand, Tejasvi; Saxena, Saurabh et al.

2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. 6858446 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nandwana, RK, Anand, T, Saxena, S, Kim, SJ, Talegaonkar, M, Elkholy, A, Choi, WS, Elshazly, A & Hanumolu, PK 2014, A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. in 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers., 6858446, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., 28th IEEE Symposium on VLSI Circuits, VLSIC 2014, Honolulu, HI, United States, 6/10/14. https://doi.org/10.1109/VLSIC.2014.6858446

Nandwana RK, Anand T, Saxena S, Kim SJ, Talegaonkar M, Elkholy A et al. A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2014. 6858446. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2014.6858446

Nandwana, Romesh Kumar ; Anand, Tejasvi ; Saxena, Saurabh et al. / A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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abstract = "A calibration-free ring oscillator based fractional-N clock multiplier using hybrid phase/current-mode phase interpolator is presented. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25GHz-to-4.75GHz with in-band noise floor of-104dBc/Hz and 1.5ps integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of-225.8dB.",

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AU - Elkholy, Ahmed

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AB - A calibration-free ring oscillator based fractional-N clock multiplier using hybrid phase/current-mode phase interpolator is presented. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25GHz-to-4.75GHz with in-band noise floor of-104dBc/Hz and 1.5ps integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of-225.8dB.

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A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement

Abstract

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