A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop

Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 4.2 GHz integer-N PLL frequency synthesizer for WLANs is described. An analog split tuned LC-VCO is controlled by coarse and fine loops to achieve both a large frequency tuning range and a small VCO gain. An averaging varactor is employed to reduce the amplitude sensitivity of the varactor, thereby reducing the AM-to-FM noise conversion. A new adaptively tuned switched capacitor integrator is used in the coarse loop for a fast lock time. The prototype test chip in a 0.13-μm CMOS process has a measured phase noise of-110dBc/Hz at 1 MHz offset, and a settling time of 50's.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages547-550
Number of pages4
ISBN (Electronic)1424407869, 9781424407866
DOIs
StatePublished - Jan 1 2007
Externally publishedYes
Event29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States
Duration: Sep 16 2007Sep 19 2007

Publication series

NameProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Other

Other29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
CountryUnited States
CitySan Jose
Period9/16/079/19/07

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Wu, T., Hanumolu, P. K., Mayaram, K., & Moon, U. K. (2007). A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 547-550). [4405791] (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405791