A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop

Ting Wu; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un Ku Moon

doi:10.1109/CICC.2007.4405791

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop

Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 4.2 GHz integer-N PLL frequency synthesizer for WLANs is described. An analog split tuned LC-VCO is controlled by coarse and fine loops to achieve both a large frequency tuning range and a small VCO gain. An averaging varactor is employed to reduce the amplitude sensitivity of the varactor, thereby reducing the AM-to-FM noise conversion. A new adaptively tuned switched capacitor integrator is used in the coarse loop for a fast lock time. The prototype test chip in a 0.13-μm CMOS process has a measured phase noise of-110dBc/Hz at 1 MHz offset, and a settling time of 50's.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	547-550
Number of pages	4
ISBN (Electronic)	1424407869, 9781424407866
DOIs	https://doi.org/10.1109/CICC.2007.4405791
State	Published - 2007
Externally published	Yes
Event	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States Duration: Sep 16 2007 → Sep 19 2007

Publication series

Name	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Other

Other	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
Country/Territory	United States
City	San Jose
Period	9/16/07 → 9/19/07

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/CICC.2007.4405791

Library availability

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Wu, T., Hanumolu, P. K., Mayaram, K., & Moon, U. K. (2007). A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 547-550). Article 4405791 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405791

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. / Wu, Ting; Hanumolu, Pavan Kumar; Mayaram, Kartikeya et al.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. p. 547-550 4405791 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wu, T, Hanumolu, PK, Mayaram, K & Moon, UK 2007, A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. in Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007., 4405791, Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, Institute of Electrical and Electronics Engineers Inc., pp. 547-550, 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007, San Jose, United States, 9/16/07. https://doi.org/10.1109/CICC.2007.4405791

Wu T, Hanumolu PK, Mayaram K, Moon UK. A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc. 2007. p. 547-550. 4405791. (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). doi: 10.1109/CICC.2007.4405791

Wu, Ting ; Hanumolu, Pavan Kumar ; Mayaram, Kartikeya et al. / A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 547-550 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

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abstract = "A 4.2 GHz integer-N PLL frequency synthesizer for WLANs is described. An analog split tuned LC-VCO is controlled by coarse and fine loops to achieve both a large frequency tuning range and a small VCO gain. An averaging varactor is employed to reduce the amplitude sensitivity of the varactor, thereby reducing the AM-to-FM noise conversion. A new adaptively tuned switched capacitor integrator is used in the coarse loop for a fast lock time. The prototype test chip in a 0.13-μm CMOS process has a measured phase noise of-110dBc/Hz at 1 MHz offset, and a settling time of 50's.",

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AB - A 4.2 GHz integer-N PLL frequency synthesizer for WLANs is described. An analog split tuned LC-VCO is controlled by coarse and fine loops to achieve both a large frequency tuning range and a small VCO gain. An averaging varactor is employed to reduce the amplitude sensitivity of the varactor, thereby reducing the AM-to-FM noise conversion. A new adaptively tuned switched capacitor integrator is used in the coarse loop for a fast lock time. The prototype test chip in a 0.13-μm CMOS process has a measured phase noise of-110dBc/Hz at 1 MHz offset, and a settling time of 50's.

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A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop

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