A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS

Sachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A deterministic digital background calibration technique to correct non-linearity in VCO-based ADCs is presented. Implemented in 90nm CMOS process, on-chip calibration improves SFDR of the prototype ADC from 46dB to more than 83dB. The ADC consumes 4.1mW power and achieves 73.9dB SNDR in 5MHz signal bandwidth.

Original languageEnglish (US)
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
StatePublished - Sep 17 2013
Externally publishedYes
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: Jun 12 2013Jun 14 2013

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period6/12/136/14/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Rao, S., Reddy, K., Young, B., & Hanumolu, P. K. (2013). A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers [6578723] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).