A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS

Sachin Rao; Karthikeyan Reddy; Brian Young; Pavan Kumar Hanumolu

A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS

Sachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A deterministic digital background calibration technique to correct non-linearity in VCO-based ADCs is presented. Implemented in 90nm CMOS process, on-chip calibration improves SFDR of the prototype ADC from 46dB to more than 83dB. The ADC consumes 4.1mW power and achieves 73.9dB SNDR in 5MHz signal bandwidth.

Original language	English (US)
Title of host publication	2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
Pages	C68-C69
State	Published - 2013
Externally published	Yes
Event	2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan Duration: Jun 12 2013 → Jun 14 2013

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2013 Symposium on VLSI Circuits, VLSIC 2013
Country/Territory	Japan
City	Kyoto
Period	6/12/13 → 6/14/13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS. / Rao, Sachin; Reddy, Karthikeyan; Young, Brian et al.

2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. p. C68-C69 6578723 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Rao, S, Reddy, K, Young, B & Hanumolu, PK 2013, A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS. in 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers., 6578723, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. C68-C69, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 6/12/13.

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abstract = "A deterministic digital background calibration technique to correct non-linearity in VCO-based ADCs is presented. Implemented in 90nm CMOS process, on-chip calibration improves SFDR of the prototype ADC from 46dB to more than 83dB. The ADC consumes 4.1mW power and achieves 73.9dB SNDR in 5MHz signal bandwidth.",

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A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS

Abstract

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