Abstract
The design and measured performance of a 40 Gb/s integrated differential PIN+TIA with DC offset control using InP single heterojunction bipolar transistors (SHBT) technology were described. The circuit was designed to handle large average optical input power levels encountered in short-haul networks where optical gain control may not be available or economical. The on-wafer, temperature-dependent s-parameter measurements were performed on the SHBTs from 1-50 GHz.
| Original language | English (US) |
|---|---|
| Pages | 59-62 |
| Number of pages | 4 |
| State | Published - 2002 |
| Event | Proceedings of the 2002 24th Annual IEEE Gallium Arsenide Integrated Circuit Symposium (IEEE GaAs IC Symposium) - Monterey, CA, United States Duration: Oct 20 2002 → Oct 23 2002 |
Other
| Other | Proceedings of the 2002 24th Annual IEEE Gallium Arsenide Integrated Circuit Symposium (IEEE GaAs IC Symposium) |
|---|---|
| Country/Territory | United States |
| City | Monterey, CA |
| Period | 10/20/02 → 10/23/02 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering