A 40 Gb/s integrated differential PIN+TIA with DC offset control using InP SHBT technology

D. Caruth, S. C. Shen, D. Chan, Milton Feng, Jose E Schutt-Aine

Research output: Contribution to conferencePaper

Abstract

The design and measured performance of a 40 Gb/s integrated differential PIN+TIA with DC offset control using InP single heterojunction bipolar transistors (SHBT) technology were described. The circuit was designed to handle large average optical input power levels encountered in short-haul networks where optical gain control may not be available or economical. The on-wafer, temperature-dependent s-parameter measurements were performed on the SHBTs from 1-50 GHz.

Original languageEnglish (US)
Pages59-62
Number of pages4
StatePublished - Jan 1 2002
EventProceedings of the 2002 24th Annual IEEE Gallium Arsenide Integrated Circuit Symposium (IEEE GaAs IC Symposium) - Monterey, CA, United States
Duration: Oct 20 2002Oct 23 2002

Other

OtherProceedings of the 2002 24th Annual IEEE Gallium Arsenide Integrated Circuit Symposium (IEEE GaAs IC Symposium)
CountryUnited States
CityMonterey, CA
Period10/20/0210/23/02

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Caruth, D., Shen, S. C., Chan, D., Feng, M., & Schutt-Aine, J. E. (2002). A 40 Gb/s integrated differential PIN+TIA with DC offset control using InP SHBT technology. 59-62. Paper presented at Proceedings of the 2002 24th Annual IEEE Gallium Arsenide Integrated Circuit Symposium (IEEE GaAs IC Symposium), Monterey, CA, United States.