A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

Guanghua Shu, Woo Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Contribution to journalArticle

Abstract

A continuous-rate digital clock and data recovery (CDR) with automatic frequency acquisition is presented. The proposed automatic frequency acquisition scheme implemented using a conventional bang-bang phase detector (BBPD) requires minimum additional hardware, is immune to input data transition density, and is applicable to subrate CDRs. A ring-oscillator-based two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs. The CDR is implemented using a digital D/PLL architecture to decouple JTRAN bandwidth from jitter tolerance (JTOL) corner frequency, eliminate jitter peaking, and remove JTRAN dependence on BBPD gain. Fabricated in a 65 nm CMOS process, the prototype CDR achieves error-free operation (BER <10-12) from 4 to 10.5 Gb/s with pseudorandom binary sequence (PRBS) data sequences ranging from PRBS7 to PRBS31. The proposed automatic frequency acquisition scheme always locks the CDR loop within 1000 ppm residual frequency error in worst case. At 10 Gb/s, the CDR consumes 22.5 mW power and achieves a recovered clock long-term jitter of 2.2 psrms/24.0 pspp with PRBS31 input data. The measured JTRAN bandwidth and JTOL corner frequencies are 0.2 and 9 MHz, respectively.

Original languageEnglish (US)
Article number7362125
Pages (from-to)428-439
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume51
Issue number2
DOIs
StatePublished - Feb 1 2016

Keywords

  • Active repeater
  • automatic frequency acquisition
  • continuous-rate receivers
  • decouple JTRAN/jitter tolerance (JTOL)
  • decouple jitter transfer (JTRAN)/jitter generation (JGEN)
  • digital clock and data recovery (CDR)
  • fractional-N phase-locked loop (PLL)
  • high-speed serial link
  • jitter peaking
  • multiplying delaylocked loop
  • optical links
  • reference-less frequency-locked loop
  • supply regulator
  • wide-range digitally controlled oscillator (DCO)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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