A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC

Ahmed Elkholy; Tejasvi Anand; Woo Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu

doi:10.1109/VLSIC.2014.6858391

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC

Ahmed Elkholy, Tejasvi Anand, Woo Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A digital fractional-N PLL that employs a time amplifier based TDC and a truly fractional divider to achieve low in-band noise with a wide bandwidth of 3MHz is presented. Fabricated in 65nm CMOS process, the prototype PLL consumes 3.7mW at 4.5GHz output frequency and achieves better than-106dBc/Hz in-band noise and 490fs_rms integrated jitter. This translates to a FoM _J of-240.5dB, which is the best among the reported fractional-N PLLs.

Original language	English (US)
Title of host publication	2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781479933273
DOIs	https://doi.org/10.1109/VLSIC.2014.6858391
State	Published - 2014
Event	28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States Duration: Jun 10 2014 → Jun 13 2014

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	28th IEEE Symposium on VLSI Circuits, VLSIC 2014
Country/Territory	United States
City	Honolulu, HI
Period	6/10/14 → 6/13/14

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Online availability

10.1109/VLSIC.2014.6858391

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Elkholy, A., Anand, T., Choi, W. S., Elshazly, A., & Hanumolu, P. K. (2014). A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers Article 6858391 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2014.6858391

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC. / Elkholy, Ahmed; Anand, Tejasvi; Choi, Woo Seok et al.
2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. 6858391 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Elkholy, A, Anand, T, Choi, WS, Elshazly, A & Hanumolu, PK 2014, A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC. in 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers., 6858391, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., 28th IEEE Symposium on VLSI Circuits, VLSIC 2014, Honolulu, HI, United States, 6/10/14. https://doi.org/10.1109/VLSIC.2014.6858391

Elkholy A, Anand T, Choi WS, Elshazly A, Hanumolu PK. A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2014. 6858391. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2014.6858391

Elkholy, Ahmed ; Anand, Tejasvi ; Choi, Woo Seok et al. / A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC. 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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abstract = "A digital fractional-N PLL that employs a time amplifier based TDC and a truly fractional divider to achieve low in-band noise with a wide bandwidth of 3MHz is presented. Fabricated in 65nm CMOS process, the prototype PLL consumes 3.7mW at 4.5GHz output frequency and achieves better than-106dBc/Hz in-band noise and 490fsrms integrated jitter. This translates to a FoM J of-240.5dB, which is the best among the reported fractional-N PLLs.",

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AB - A digital fractional-N PLL that employs a time amplifier based TDC and a truly fractional divider to achieve low in-band noise with a wide bandwidth of 3MHz is presented. Fabricated in 65nm CMOS process, the prototype PLL consumes 3.7mW at 4.5GHz output frequency and achieves better than-106dBc/Hz in-band noise and 490fsrms integrated jitter. This translates to a FoM J of-240.5dB, which is the best among the reported fractional-N PLLs.

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A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC

Abstract

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