A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

Keyphrases

• Low Noise 100%
• Wide Bandwidth 100%
• Fractional-N PLL 100%
• Time Amplifier 100%
• Time-to-digital Converter 50%
• PLL Bandwidth 50%
• Fractional Divider 50%
• In-band Noise 50%
• Nonlinearity 25%
• Dynamic Range 25%
• Low Power 25%
• Proposed Architecture 25%
• Limit Cycle Behavior 25%
• Settling Behavior 25%
• Plague 25%
• CMOS Process 25%
• Integrated Jitter 25%
• High-resolution TDC 25%
• Output Frequency 25%
• Tracking Behavior 25%
• 65nm CMOS 25%
• Fast Tracking 25%
• Digital Architecture 25%
• Quantization Noise 25%
• Fast Settling 25%

Engineering

• Amplifier 100%
• Phase Locked Loop 100%
• High Resolution 11%
• Time Domain 11%
• Dynamic Range 11%
• Nonlinearity 11%
• Limit Cycle 11%
• Output Frequency 11%
• Quantization Noise 11%