A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

Ahmed Elkholy, Tejasvi Anand, Woo Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Contribution to journalArticle

Abstract

A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLLs is greatly suppressed by the TA-TDC, thus permitting wide PLL bandwidth. The proposed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than -106 dBc/Hz in-band noise and 3 MHz PLL bandwidth at 4.5 GHz output frequency using 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fsrms integrated jitter. This translates to a FoMJ of -240.5 dB, which is the best among the reported fractional-N PLLs.

Original languageEnglish (US)
Article number7027236
Pages (from-to)867-881
Number of pages15
JournalIEEE Journal of Solid-State Circuits
Volume50
Issue number4
DOIs
StatePublished - Apr 1 2015

Keywords

  • ADPLL
  • BBPD
  • DTC
  • LMS
  • Phase-locked loops (PLLs)
  • TDC
  • digital PLL
  • digitally controlled oscillator (DCO)
  • fractional divider
  • fractional-N
  • frequency synthesizer
  • jitter
  • time amplifier
  • wide bandwidth

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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