A 3.6-mW 50-MHz PN code acquisition filter via statistical error compensation in 180-nm CMOS

Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Naresh R Shanbhag, Douglas L Jones

Research output: Contribution to journalArticle

Abstract

In this brief, we present a novel architecture for pseudorandom (PN) code acquisition based on statistical error compensation (SEC), which achieves significant power savings. SEC treats errors in hardware as noise in communication networks, and employs robust estimation theory to compensate for errors. We apply SEC to a 256-tap PN code acquisition filter in a 180- nm CMOS process. Multiple (five) dies were tested under voltage overscaling to achieve a near constant detection probability (Pdet) above 90%. The minimum energy consumption ranged from 72.89 to 210.59 pJ (ave 122.52 pJ) for supply voltages between 0.69 and 0.70 V. These operating conditions result in raw error rates of 85.83%-91.23% (ave 88.99%). Energy savings over a conventional error-free design ranges from 2.4x to 5.8x (ave 3.86x ). Energy savings over past work ranges from 1.55x to 3.79x (ave 2.52x). Improvement in error-tolerance over existing error-tolerant designs range from 2146x to 2281x (ave 2225x). The large energy savings were found to be due to a combination of voltage scaling and activity factor reduction. The proposed design achieves a 2.5x improvement in the figure of merit [normalized power/(#taps ∗ precision ∗ sample rate)] compared with conventional PN code acquisition filters.

Original languageEnglish (US)
Article number6804020
Pages (from-to)598-602
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number3
DOIs
StatePublished - Mar 1 2015

Fingerprint

Error compensation
Energy conservation
Electric potential
Telecommunication networks
Energy utilization
Hardware

Keywords

  • Error tolerance
  • low power
  • pseudorandom (PN) code acquisition
  • statistical error compensation (SEC)
  • voltage overscaling (VOS)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

A 3.6-mW 50-MHz PN code acquisition filter via statistical error compensation in 180-nm CMOS. / Kim, Eric P.; Baker, Daniel J.; Narayanan, Sriram; Shanbhag, Naresh R; Jones, Douglas L.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 3, 6804020, 01.03.2015, p. 598-602.

Research output: Contribution to journalArticle

@article{ddafc15f037646dfaffd245ffc8ed95d,
title = "A 3.6-mW 50-MHz PN code acquisition filter via statistical error compensation in 180-nm CMOS",
abstract = "In this brief, we present a novel architecture for pseudorandom (PN) code acquisition based on statistical error compensation (SEC), which achieves significant power savings. SEC treats errors in hardware as noise in communication networks, and employs robust estimation theory to compensate for errors. We apply SEC to a 256-tap PN code acquisition filter in a 180- nm CMOS process. Multiple (five) dies were tested under voltage overscaling to achieve a near constant detection probability (Pdet) above 90{\%}. The minimum energy consumption ranged from 72.89 to 210.59 pJ (ave 122.52 pJ) for supply voltages between 0.69 and 0.70 V. These operating conditions result in raw error rates of 85.83{\%}-91.23{\%} (ave 88.99{\%}). Energy savings over a conventional error-free design ranges from 2.4x to 5.8x (ave 3.86x ). Energy savings over past work ranges from 1.55x to 3.79x (ave 2.52x). Improvement in error-tolerance over existing error-tolerant designs range from 2146x to 2281x (ave 2225x). The large energy savings were found to be due to a combination of voltage scaling and activity factor reduction. The proposed design achieves a 2.5x improvement in the figure of merit [normalized power/(#taps ∗ precision ∗ sample rate)] compared with conventional PN code acquisition filters.",
keywords = "Error tolerance, low power, pseudorandom (PN) code acquisition, statistical error compensation (SEC), voltage overscaling (VOS)",
author = "Kim, {Eric P.} and Baker, {Daniel J.} and Sriram Narayanan and Shanbhag, {Naresh R} and Jones, {Douglas L}",
year = "2015",
month = "3",
day = "1",
doi = "10.1109/TVLSI.2014.2311318",
language = "English (US)",
volume = "23",
pages = "598--602",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

TY - JOUR

T1 - A 3.6-mW 50-MHz PN code acquisition filter via statistical error compensation in 180-nm CMOS

AU - Kim, Eric P.

AU - Baker, Daniel J.

AU - Narayanan, Sriram

AU - Shanbhag, Naresh R

AU - Jones, Douglas L

PY - 2015/3/1

Y1 - 2015/3/1

N2 - In this brief, we present a novel architecture for pseudorandom (PN) code acquisition based on statistical error compensation (SEC), which achieves significant power savings. SEC treats errors in hardware as noise in communication networks, and employs robust estimation theory to compensate for errors. We apply SEC to a 256-tap PN code acquisition filter in a 180- nm CMOS process. Multiple (five) dies were tested under voltage overscaling to achieve a near constant detection probability (Pdet) above 90%. The minimum energy consumption ranged from 72.89 to 210.59 pJ (ave 122.52 pJ) for supply voltages between 0.69 and 0.70 V. These operating conditions result in raw error rates of 85.83%-91.23% (ave 88.99%). Energy savings over a conventional error-free design ranges from 2.4x to 5.8x (ave 3.86x ). Energy savings over past work ranges from 1.55x to 3.79x (ave 2.52x). Improvement in error-tolerance over existing error-tolerant designs range from 2146x to 2281x (ave 2225x). The large energy savings were found to be due to a combination of voltage scaling and activity factor reduction. The proposed design achieves a 2.5x improvement in the figure of merit [normalized power/(#taps ∗ precision ∗ sample rate)] compared with conventional PN code acquisition filters.

AB - In this brief, we present a novel architecture for pseudorandom (PN) code acquisition based on statistical error compensation (SEC), which achieves significant power savings. SEC treats errors in hardware as noise in communication networks, and employs robust estimation theory to compensate for errors. We apply SEC to a 256-tap PN code acquisition filter in a 180- nm CMOS process. Multiple (five) dies were tested under voltage overscaling to achieve a near constant detection probability (Pdet) above 90%. The minimum energy consumption ranged from 72.89 to 210.59 pJ (ave 122.52 pJ) for supply voltages between 0.69 and 0.70 V. These operating conditions result in raw error rates of 85.83%-91.23% (ave 88.99%). Energy savings over a conventional error-free design ranges from 2.4x to 5.8x (ave 3.86x ). Energy savings over past work ranges from 1.55x to 3.79x (ave 2.52x). Improvement in error-tolerance over existing error-tolerant designs range from 2146x to 2281x (ave 2225x). The large energy savings were found to be due to a combination of voltage scaling and activity factor reduction. The proposed design achieves a 2.5x improvement in the figure of merit [normalized power/(#taps ∗ precision ∗ sample rate)] compared with conventional PN code acquisition filters.

KW - Error tolerance

KW - low power

KW - pseudorandom (PN) code acquisition

KW - statistical error compensation (SEC)

KW - voltage overscaling (VOS)

UR - http://www.scopus.com/inward/record.url?scp=85027929062&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85027929062&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2014.2311318

DO - 10.1109/TVLSI.2014.2311318

M3 - Article

AN - SCOPUS:85027929062

VL - 23

SP - 598

EP - 602

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 3

M1 - 6804020

ER -