A 3.6-mW 50-MHz PN code acquisition filter via statistical error compensation in 180-nm CMOS

Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Naresh R. Shanbhag, Douglas L Jones

Research output: Contribution to journalArticlepeer-review


In this brief, we present a novel architecture for pseudorandom (PN) code acquisition based on statistical error compensation (SEC), which achieves significant power savings. SEC treats errors in hardware as noise in communication networks, and employs robust estimation theory to compensate for errors. We apply SEC to a 256-tap PN code acquisition filter in a 180- nm CMOS process. Multiple (five) dies were tested under voltage overscaling to achieve a near constant detection probability (Pdet) above 90%. The minimum energy consumption ranged from 72.89 to 210.59 pJ (ave 122.52 pJ) for supply voltages between 0.69 and 0.70 V. These operating conditions result in raw error rates of 85.83%-91.23% (ave 88.99%). Energy savings over a conventional error-free design ranges from 2.4x to 5.8x (ave 3.86x ). Energy savings over past work ranges from 1.55x to 3.79x (ave 2.52x). Improvement in error-tolerance over existing error-tolerant designs range from 2146x to 2281x (ave 2225x). The large energy savings were found to be due to a combination of voltage scaling and activity factor reduction. The proposed design achieves a 2.5x improvement in the figure of merit [normalized power/(#taps ∗ precision ∗ sample rate)] compared with conventional PN code acquisition filters.

Original languageEnglish (US)
Article number6804020
Pages (from-to)598-602
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number3
StatePublished - Mar 1 2015
Externally publishedYes


  • Error tolerance
  • low power
  • pseudorandom (PN) code acquisition
  • statistical error compensation (SEC)
  • voltage overscaling (VOS)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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