Monolithic frequency references built using on-chip time constants are gaining popularity as possible replacements to bulky quartz-crystal or MEMS-based oscillators in low-cost applications. Among them, RC time-constant-based references - are most attractive because they occupy a small area, consume little power, and are well suited for integration in any standard CMOS process. But their performance is very susceptible to variations in temperature and supply voltage. Frequency-locked-loop(FLL)-based closed-loop RC oscillators -, compared to open-loop relaxation oscillators, have higher immunity to voltage variations. However, their performance is also limited by the temperature dependence of the resistor. This limitation was addressed in the prior art by using a composite resistor made from resistors with opposing temperature coefficients (TCs) . Unfortunately, the TC of the composite resistor is highly dependent on process-sensitive sheet resistance of resistors comprising it. So, it is typically implemented using a vast array of resistors that are trimmed on a sample-by-sample basis. While this approach helps to alleviate process sensitivity, two critical factors limit the achievable frequency inaccuracy to about 5000ppm. First, the accuracy with which the TC is canceled across process corners is fundamentally limited by the finite number of resistor combinations that can be practically implemented on a chip. Second, leakage currents in the switches used to select the resistors along with the mixing of TCs of individual resistors in the array generate large higher-order TCs that are difficult to compensate. Recently reported voltage-ratio adjusting  and polynomial-based  higher-order compensation schemes lowered frequency inaccuracy to about 500ppm. However, they either rely on precise combinations of analog voltages and are therefore sensitive to circuit-level imperfections or occupy a large area and exhibit poor power efficiency (100μW/MHz) .