Serial I/O interfaces consist of many SerDes cores integrated on a single ASIC to meet the data throughput demands of modern digital computer systems. The narrow lane spacing between the tightly integrated SerDes cores causes inevitable electromagnetic (EM) coupling between the inductors used in LC oscillators, which becomes more pronounced when the adjacent lanes are operating at slightly different data rates. In such scenarios, ring-oscillator (RO) based synthesizers become very attractive as they offer many advantages over their LC-oscillator counterparts. They provide wide tuning range, occupy smaller area, provide multi-phase clocks, and are less susceptible to EM coupling. While these attributes are appealing, their poor phase noise performance has precluded their usage in high data rate applications.