A 3.2GHz 405fsrmsjitter-237.2dB-FoMJITring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction

Ahmed Elmallah, Junheng Zhu, Amr Khashaba, Karim Megawer, Ahmed Elkholy, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Serial I/O interfaces consist of many SerDes cores integrated on a single ASIC to meet the data throughput demands of modern digital computer systems. The narrow lane spacing between the tightly integrated SerDes cores causes inevitable electromagnetic (EM) coupling between the inductors used in LC oscillators, which becomes more pronounced when the adjacent lanes are operating at slightly different data rates. In such scenarios, ring-oscillator (RO) based synthesizers become very attractive as they offer many advantages over their LC-oscillator counterparts. They provide wide tuning range, occupy smaller area, provide multi-phase clocks, and are less susceptible to EM coupling. While these attributes are appealing, their poor phase noise performance has precluded their usage in high data rate applications.

Original languageEnglish (US)
Title of host publication2021 IEEE Custom Integrated Circuits Conference, CICC 2021 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728175812
DOIs
StatePublished - Apr 2021
Event2021 IEEE Custom Integrated Circuits Conference, CICC 2021 - Virtual, Austin, United States
Duration: Apr 25 2021Apr 30 2021

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2021-April
ISSN (Print)0886-5930

Conference

Conference2021 IEEE Custom Integrated Circuits Conference, CICC 2021
Country/TerritoryUnited States
CityVirtual, Austin
Period4/25/214/30/21

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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