@inproceedings{6ad4e30871874677817d3ade7d07bbf1,
title = "A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance",
abstract = "A 3.2Gbps CDR circuit employs an oversampling architecture to decouple the tradeoff between jitter generation and jitter tolerance. The test chip fabricated in a 0.13μm CMOS process achieves a 30x increase in the jitter tolerance corner without increasing recovered clock jitter. Power consumption is 19.5mW from a 1.4V supply at 3.2Gbps and die area is 0.081mm2.",
author = "Merrick Brownlee and Hanumolu, {Pavan Kumar} and Moon, {Un Ku}",
year = "2007",
doi = "10.1109/CICC.2007.4405751",
language = "English (US)",
series = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "353--356",
booktitle = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007",
address = "United States",
note = "29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 ; Conference date: 16-09-2007 Through 19-09-2007",
}