A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance

Merrick Brownlee; Pavan Kumar Hanumolu; Un Ku Moon

doi:10.1109/CICC.2007.4405751

A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance

Merrick Brownlee, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 3.2Gbps CDR circuit employs an oversampling architecture to decouple the tradeoff between jitter generation and jitter tolerance. The test chip fabricated in a 0.13μm CMOS process achieves a 30x increase in the jitter tolerance corner without increasing recovered clock jitter. Power consumption is 19.5mW from a 1.4V supply at 3.2Gbps and die area is 0.081mm².

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	353-356
Number of pages	4
ISBN (Electronic)	1424407869, 9781424407866
DOIs	https://doi.org/10.1109/CICC.2007.4405751
State	Published - Jan 1 2007
Externally published	Yes
Event	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States Duration: Sep 16 2007 → Sep 19 2007

Publication series

Name	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Other

Other	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
Country/Territory	United States
City	San Jose
Period	9/16/07 → 9/19/07

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2007.4405751

Cite this

Brownlee, M., Hanumolu, P. K., & Moon, U. K. (2007). A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 353-356). [4405751] (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405751

A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. / Brownlee, Merrick; Hanumolu, Pavan Kumar; Moon, Un Ku.

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. p. 353-356 4405751 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Brownlee, M, Hanumolu, PK & Moon, UK 2007, A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. in Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007., 4405751, Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, Institute of Electrical and Electronics Engineers Inc., pp. 353-356, 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007, San Jose, United States, 9/16/07. https://doi.org/10.1109/CICC.2007.4405751

Brownlee M, Hanumolu PK, Moon UK. A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc. 2007. p. 353-356. 4405751. (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). https://doi.org/10.1109/CICC.2007.4405751

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A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance

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