A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance

Merrick Brownlee, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 3.2Gbps CDR circuit employs an oversampling architecture to decouple the tradeoff between jitter generation and jitter tolerance. The test chip fabricated in a 0.13μm CMOS process achieves a 30x increase in the jitter tolerance corner without increasing recovered clock jitter. Power consumption is 19.5mW from a 1.4V supply at 3.2Gbps and die area is 0.081mm2.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages353-356
Number of pages4
ISBN (Electronic)1424407869, 9781424407866
DOIs
StatePublished - Jan 1 2007
Externally publishedYes
Event29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States
Duration: Sep 16 2007Sep 19 2007

Publication series

NameProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Other

Other29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
CountryUnited States
CitySan Jose
Period9/16/079/19/07

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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