A 3.2-GHz 405 fsrms Jitter -237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer

Ahmed Elmallah, Junheng Zhu, Amr Khashaba, Karim M. Megawer, Ahmed Elkholy, Pavan Kumar Hanumolu

Research output: Contribution to journalArticlepeer-review


A ring-oscillator (RO)-based low-jitter digital fractional-N frequency synthesizer is presented. It employs a frequency doubler (FD) that doubles the reference clock frequency, a 2-bit time-to-digital converter (TDC) with optimized thresholds to minimize the quantization error, and a high-resolution digital-to-time converter (DTC) to cancel the quantization error of the delta-sigma fractional divider (FDIV). DTC's linearity is improved using a piecewise linear (PWL) function-based correction scheme. On-chip digital calibration is extensively used to correct imperfections of the FD, TDC, and DTC. A prototype synthesizer incorporating the proposed techniques and implemented in a 65-nm CMOS produces a 3.2-GHz output clock from a 96-MHz input clock. The worst-case integrated jitter is 306 and 405 fs in integer and fractional-N modes, respectively. The synthesizer consumes 11.7 mW from a 1-V supply of which 7.84 mW is consumed by the oscillator. The jitter figure-of-merit of the synthesizer is -237.2 dB.

Original languageEnglish (US)
Pages (from-to)698-708
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Issue number3
StatePublished - Mar 1 2022
Externally publishedYes


  • Fractional-N
  • high-resolution digital-to-time converter (DTC)
  • optimum-threshold time-to-digital converter (TDC)
  • piecewise linear (PWL) nonlinearity correction
  • quantization error cancellation (QEC)
  • ring voltage-controlled oscillator (VCO)
  • serializer-deserializer (SerDes)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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