A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS

Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Serial link transceivers that can operate across a wide range of data rates offer flexibility and rapid realization of single-chip multi-standard solutions. The ability to independently control the data rate of each lane in a multi-lane transceiver with fine granularity is also valuable [1,2]. The implementation of such transceivers would require analog front-ends and clocking circuits that can operate over a wide range of frequencies. As a result, compared to transceivers that are optimized to operate at one single data rate, flexible-rate transceivers are power and area hungry [1]. Because a single PLL cannot generate clocks across the entire interface operating range, [1,2] use multiple LC tanks, carefully optimized waveform shaping circuits, power hungry clock distribution, and complex frequency planning methods.

Original languageEnglish (US)
Title of host publication2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
EditorsLaura C. Fujino
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages492-493
Number of pages2
ISBN (Electronic)9781509037575
DOIs
StatePublished - Mar 2 2017
Event64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States
Duration: Feb 5 2017Feb 9 2017

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume60
ISSN (Print)0193-6530

Other

Other64th IEEE International Solid-State Circuits Conference, ISSCC 2017
CountryUnited States
CitySan Francisco
Period2/5/172/9/17

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Nandwana, R. K., Saxena, S., Elkholy, A., Talegaonkar, M., Zhu, J., Choi, W. S., Elmallah, A., & Hanumolu, P. K. (2017). A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. In L. C. Fujino (Ed.), 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017 (pp. 492-493). [7870476] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 60). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2017.7870476