A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS

Saurabh Saxena; Guanghua Shu; Romesh Kumar Nandwana; Mrunmay Talegaonkar; Ahmed Elkholy; Tejasvi Anand; Seong Joong Kim; Woo Seok Choi; Pavan Kumar Hanumolu

doi:10.1109/VLSIC.2015.7231320

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS

Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo Seok Choi, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<10^-12 while operating at 14Gb/s with 12dB channel loss.

Original language	English (US)
Title of host publication	2015 Symposium on VLSI Circuits, VLSI Circuits 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C352-C353
ISBN (Electronic)	9784863485020
DOIs	https://doi.org/10.1109/VLSIC.2015.7231320
State	Published - Aug 31 2015
Event	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan Duration: Jun 17 2015 → Jun 19 2015

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2015-August

Other

Other	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
Country/Territory	Japan
City	Kyoto
Period	6/17/15 → 6/19/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Online availability

10.1109/VLSIC.2015.7231320

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Saxena, S., Shu, G., Nandwana, R. K., Talegaonkar, M., Elkholy, A., Anand, T., Kim, S. J., Choi, W. S., & Hanumolu, P. K. (2015). A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015 (pp. C352-C353). [7231320] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231320

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. / Saxena, Saurabh; Shu, Guanghua; Nandwana, Romesh Kumar et al.

2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. C352-C353 7231320 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Saxena, S, Shu, G, Nandwana, RK, Talegaonkar, M, Elkholy, A, Anand, T, Kim, SJ, Choi, WS & Hanumolu, PK 2015, A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. in 2015 Symposium on VLSI Circuits, VLSI Circuits 2015., 7231320, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. C352-C353, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, Kyoto, Japan, 6/17/15. https://doi.org/10.1109/VLSIC.2015.7231320

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abstract = "A low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<10-12 while operating at 14Gb/s with 12dB channel loss.",

author = "Saurabh Saxena and Guanghua Shu and Nandwana, {Romesh Kumar} and Mrunmay Talegaonkar and Ahmed Elkholy and Tejasvi Anand and Kim, {Seong Joong} and Choi, {Woo Seok} and Hanumolu, {Pavan Kumar}",

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AB - A low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<10-12 while operating at 14Gb/s with 12dB channel loss.

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A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS

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