A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS

Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo Seok Choi, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<10-12 while operating at 14Gb/s with 12dB channel loss.

Original languageEnglish (US)
Title of host publication2015 Symposium on VLSI Circuits, VLSI Circuits 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC352-C353
ISBN (Electronic)9784863485020
DOIs
StatePublished - Aug 31 2015
Event29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan
Duration: Jun 17 2015Jun 19 2015

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2015-August

Other

Other29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
CountryJapan
CityKyoto
Period6/17/156/19/15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Saxena, S., Shu, G., Nandwana, R. K., Talegaonkar, M., Elkholy, A., Anand, T., Kim, S. J., Choi, W. S., & Hanumolu, P. K. (2015). A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015 (pp. C352-C353). [7231320] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231320