Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm2 IC is implemented in a 1.8-V 0.18-μm CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an energy-efficiency of 2. 36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18-/μm designs with the smallest area; and 3) comparable throughput with an area reduction of 3-4.3 × with reference to a look-ahead based high-speed design (Radix-4 design), and a parallel architecture.

Original languageEnglish (US)
Pages (from-to)1718-1724
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Issue number8
StatePublished - Aug 2005


  • CMOS
  • Iterative processing
  • Maximum a posteriori probability (MAP) decoder
  • Pipeline
  • Turbo decoder
  • Turbo equalizer

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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