A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver

Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo Seok Choi, Pavan Kumar Hanumolu

Research output: Contribution to journalArticle

Abstract

Design techniques to improve energy efficiency of serial link transceivers are presented. Power consumption is reduced by using: 1) low-power clock generation, recovery, and distribution schemes; 2) charge-based circuits to implement analog front-end and samplers/flip-flops; and 3) a partially segmented voltage-mode (VM) output driver. An LC-oscillator based digital phase-locked loop (PLL) is used to generate a low jitter clock that is shared between the transmitter (Tx) and receiver (Rx). The clock recovery unit uses a local ring-oscillator based PLL to reduce the number of phase interpolators and the amount of high-frequency clock distribution. Charge-based samplers that were shown to operate with limited return-to-zero voltage swings and consume only dynamic power are modified to provide non-return-to-zero outputs and used extensively in the deserializer and Rx front-end circuits. A partially segmented VM output driver with embedded 2-tap de-emphasis is proposed to reduce power consumption of pre-drivers. Fabricated in a 65 nm CMOS process, the 14 Gb/s transceiver prototype employs aforementioned techniques and achieves an energy efficiency of 2.8 mW/Gb/s. The Tx achieves a phase margin of 0.36 UI (BER = 10-12) at the end of an 11 dB loss channel with an energy efficiency of 0.89 mW/Gb/s. The Rx recovers clock with 1.8 psrms long term absolute jitter at BER < 10-12 and achieves an energy efficiency of 1.69 mW/Gb/s. The LC-oscillator based digital PLL achieves an integrated jitter of 0.605 psrms with an energy efficiency of 0.5 mW/GHz at 7 GHz output frequency.

Original languageEnglish (US)
Article number7890481
Pages (from-to)1399-1411
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Volume52
Issue number5
DOIs
StatePublished - May 2017

Keywords

  • Charge-based flip-flop (CFF)
  • digital clock and data recovery (CDR)
  • voltage-mode (VM) transmitter (Tx)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Saxena, S., Shu, G., Nandwana, R. K., Talegaonkar, M., Elkholy, A., Anand, T., Choi, W. S., & Hanumolu, P. K. (2017). A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE Journal of Solid-State Circuits, 52(5), 1399-1411. [7890481]. https://doi.org/10.1109/JSSC.2016.2645738