A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC

Romesh Kumar Nandwana; Saurabh Saxena; Amr Elshazly; Kartikeya Mayaram; Pavan Kumar Hanumolu

A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC

Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A scrambling TDC is proposed to mitigate dithering jitter accumulation in clock multipliers with low reference frequencies. Fabricated in a 90nm CMOS process, the prototype operates with a 1.25MHz reference clock and generates 160MHz and 2.56GHz output clocks with a long-term absolute jitter of 2.7ps _rms and 6.28ps_rms, respectively.

Original language	English (US)
Title of host publication	2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
Pages	C156-C157
State	Published - 2013
Externally published	Yes
Event	2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan Duration: Jun 12 2013 → Jun 14 2013

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2013 Symposium on VLSI Circuits, VLSIC 2013
Country/Territory	Japan
City	Kyoto
Period	6/12/13 → 6/14/13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Library availability

Discover UIUC Full Text

Cite this

A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC. / Nandwana, Romesh Kumar; Saxena, Saurabh; Elshazly, Amr et al.

2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. p. C156-C157 6578645 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nandwana, RK, Saxena, S, Elshazly, A, Mayaram, K & Hanumolu, PK 2013, A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC. in 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers., 6578645, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. C156-C157, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 6/12/13.

@inproceedings{03ca5d08a1ed45f0a98727651e65dc07,

title = "A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC",

abstract = "A scrambling TDC is proposed to mitigate dithering jitter accumulation in clock multipliers with low reference frequencies. Fabricated in a 90nm CMOS process, the prototype operates with a 1.25MHz reference clock and generates 160MHz and 2.56GHz output clocks with a long-term absolute jitter of 2.7ps rms and 6.28psrms, respectively.",

author = "Nandwana, {Romesh Kumar} and Saurabh Saxena and Amr Elshazly and Kartikeya Mayaram and Hanumolu, {Pavan Kumar}",

year = "2013",

language = "English (US)",

isbn = "9784863483484",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "C156--C157",

booktitle = "2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers",

note = "2013 Symposium on VLSI Circuits, VLSIC 2013 ; Conference date: 12-06-2013 Through 14-06-2013",

}

TY - GEN

T1 - A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC

AU - Nandwana, Romesh Kumar

AU - Saxena, Saurabh

AU - Elshazly, Amr

AU - Mayaram, Kartikeya

AU - Hanumolu, Pavan Kumar

PY - 2013

Y1 - 2013

N2 - A scrambling TDC is proposed to mitigate dithering jitter accumulation in clock multipliers with low reference frequencies. Fabricated in a 90nm CMOS process, the prototype operates with a 1.25MHz reference clock and generates 160MHz and 2.56GHz output clocks with a long-term absolute jitter of 2.7ps rms and 6.28psrms, respectively.

AB - A scrambling TDC is proposed to mitigate dithering jitter accumulation in clock multipliers with low reference frequencies. Fabricated in a 90nm CMOS process, the prototype operates with a 1.25MHz reference clock and generates 160MHz and 2.56GHz output clocks with a long-term absolute jitter of 2.7ps rms and 6.28psrms, respectively.

UR - http://www.scopus.com/inward/record.url?scp=84883762294&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84883762294&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84883762294

SN - 9784863483484

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - C156-C157

BT - 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers

T2 - 2013 Symposium on VLSI Circuits, VLSIC 2013

Y2 - 12 June 2013 through 14 June 2013

ER -

A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC

Abstract

Publication series

Other

ASJC Scopus subject areas

Library availability

Related links

Fingerprint

Cite this