A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC

Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A scrambling TDC is proposed to mitigate dithering jitter accumulation in clock multipliers with low reference frequencies. Fabricated in a 90nm CMOS process, the prototype operates with a 1.25MHz reference clock and generates 160MHz and 2.56GHz output clocks with a long-term absolute jitter of 2.7ps rms and 6.28psrms, respectively.

Original languageEnglish (US)
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
PagesC156-C157
StatePublished - Sep 17 2013
Externally publishedYes
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: Jun 12 2013Jun 14 2013

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period6/12/136/14/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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