Modern mobile platforms utilize power cycling to lower power dissipation and increase battery life. By turning off the circuits that are not in use, power cycling provides a viable means to make power dissipation proportional to workload, hence achieving energy proportional operation. The effectiveness of this approach is governed by the turn on/off times, off-state power dissipation, and energy overhead due to power-cycling. Ideally, the circuits must turn on/off in zero time, consume no off-state power, and incur minimal energy overhead during on-to-off and off-to-on transitions. Conventional clock multipliers implemented using phase-locked loops (PLLs) present the biggest bottleneck in achieving these performance goals due to their long locking times. Even if the PLL is frequency locked, the slow phase acquisition process limits the power-on time [1-2]. Techniques such as dynamic phase-error compensation , edge-missing compensation , and hybrid PLLs  improve the phase acquisition time to at best few hundred reference cycles. However, such improvements are inadequate to make best use of power-cycling. Multiplying injection-locked oscillators (MILO) are shown to lock faster than PLLs, but suffer from conflicting requirements on injection strength to simultaneously achieve low jitter and fast locking. Increasing the injection strength extends lock range and reduces locking time, but severely degrades the deterministic jitter performance . In view of these drawbacks, we propose a highly digital clock multiplier that seeks to achieve low jitter, fast locking, and near-zero off-state power. By using a highly scalable digital architecture with accurate frequency presetting and instantaneous phase acquisition, the prototype 8×/16× clock multiplier achieves 10ns (3 reference cycles) power-on time, 2psrms long-term absolute jitter, less than 25μW off-state power, 12pJ energy overhead for on/off transition, and 2.2mW on-state power at 2.5GHz output frequency.