A 256-Kb dual-V CC SRAM building block in 65-nm CMOS process with actively clamped sleep transistor

Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Jason Howard, Greg Ruhl, Murad Sunna, James Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De

Research output: Contribution to journalArticlepeer-review


This paper addresses the stability problem of SRAM cells used in dense last level caches (LLCs). In order for the LLC not to limit the minimum voltage at which a processor core can run, a dual-V CC 256-Kb SRAM building block is proposed. A fixed high-voltage supply powers the cache which allows the use of the smallest SRAM cell for maximum density, while a separate variable supply is used by the core for ultra-low-voltage operation using dynamic voltage and frequency (DVF). Implemented in a 65-nm bulk CMOS process, the block features low overhead embedded level shifters and an actively clamped sleep transistor for maximum cache leakage power reduction during standby. Measured results show that the proposed block runs at 4.2 GHz while consuming 30 mW at 85°C and 1.2 V supply. Furthermore, measurements across a wide range of process, voltage, temperature, and aging conditions indicate virtual ground clamping accuracy within a few millivolts of required cache standby V MIN · Extrapolating the 256-Kb block measurement results in a large 64-Mb LLC used in a dual-V CC processor gives 35% reduction in total processor power as compared with a single-V CC processor design running at a high supply voltage.

Original languageEnglish (US)
Pages (from-to)233-241
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number1
StatePublished - Jan 2007
Externally publishedYes


  • Dual-V
  • Leakage
  • SRAM
  • Sleep
  • Stability
  • Variation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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