Ring oscillator (RO)-based clock multipliers are traditionally used for clocking digital systems such as processors. While they are most commonly implemented using PLLs, it is becoming increasingly difficult to design them in a power efficient manner, as their jitter requirements grow more stringent. Recognizing that the main limitation of PLLs arises from limited RO noise suppression bandwidth (NBW = FREF/10), multiplying delay-locked loops (MDLLs) that suppress noise by replacing a RO's noisy edge with a clean reference clock edge have gained prominence [1-3]. Such an edge replacement operation suppresses RO noise with an increased NBW of about FREF/4 . However, imperfections of edge replacement logic have limited the output frequency of MDLLs [1, 2] or degraded their jitter performance at frequencies beyond 2.5GHz . Furthermore, MDLLs are susceptible to transistor non-idealities and require elaborate analog calibration schemes that are prone to circuit imperfections [2, 3]. In contrast to PLLs and MDLLs, injection-locked clock multipliers (ILCMs) lock RO frequency to an integer multiple (N) of FREF by injecting narrow pulses at FREF into the RO whose free running frequency is about NFREF . Because ILCMs do not require logic that needs to adhere to stringent timing requirements (like MDLLs) they are better suited for generating high frequencies. However, their jitter performance is limited by: (i) smaller NBW (≈ FREF/6) compared to MDLLs, (ii) limited suppression of RO flicker noise due to their Type-I response, and (iii) the need for RO free running frequency, FFR, to be close to NFREF for maintaining low jitter performance across voltage and temperature. These factors limit the multiplication factor (usually to less than 10) and degrade power efficiency [4,5]. In this paper, we present an ILCM architecture that achieves a NBW of close to FREF/3 with a jitter of 335fsrms at 5GHz, while operating with FREF = 125MHz and consuming 5.3mW.