A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS

Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Ring oscillator (RO)-based clock multipliers are traditionally used for clocking digital systems such as processors. While they are most commonly implemented using PLLs, it is becoming increasingly difficult to design them in a power efficient manner, as their jitter requirements grow more stringent. Recognizing that the main limitation of PLLs arises from limited RO noise suppression bandwidth (NBW = FREF/10), multiplying delay-locked loops (MDLLs) that suppress noise by replacing a RO's noisy edge with a clean reference clock edge have gained prominence [1-3]. Such an edge replacement operation suppresses RO noise with an increased NBW of about FREF/4 [1]. However, imperfections of edge replacement logic have limited the output frequency of MDLLs [1, 2] or degraded their jitter performance at frequencies beyond 2.5GHz [3]. Furthermore, MDLLs are susceptible to transistor non-idealities and require elaborate analog calibration schemes that are prone to circuit imperfections [2, 3]. In contrast to PLLs and MDLLs, injection-locked clock multipliers (ILCMs) lock RO frequency to an integer multiple (N) of FREF by injecting narrow pulses at FREF into the RO whose free running frequency is about NFREF [4]. Because ILCMs do not require logic that needs to adhere to stringent timing requirements (like MDLLs) they are better suited for generating high frequencies. However, their jitter performance is limited by: (i) smaller NBW (≈ FREF/6) compared to MDLLs, (ii) limited suppression of RO flicker noise due to their Type-I response, and (iii) the need for RO free running frequency, FFR, to be close to NFREF for maintaining low jitter performance across voltage and temperature. These factors limit the multiplication factor (usually to less than 10) and degrade power efficiency [4,5]. In this paper, we present an ILCM architecture that achieves a NBW of close to FREF/3 with a jitter of 335fsrms at 5GHz, while operating with FREF = 125MHz and consuming 5.3mW.

Original languageEnglish (US)
Title of host publication2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
EditorsLaura C. Fujino
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages152-153
Number of pages2
ISBN (Electronic)9781509037575
DOIs
StatePublished - Mar 2 2017
Event64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States
Duration: Feb 5 2017Feb 9 2017

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume60
ISSN (Print)0193-6530

Other

Other64th IEEE International Solid-State Circuits Conference, ISSCC 2017
CountryUnited States
CitySan Francisco
Period2/5/172/9/17

Fingerprint

Jitter
Clocks
Phase locked loops
Spurious signal noise
Defects
Transistors
Calibration
Bandwidth
Networks (circuits)
Electric potential
Temperature

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Coombs, D., Elkholy, A., Nandwana, R. K., Elmallah, A., & Hanumolu, P. K. (2017). A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. In L. C. Fujino (Ed.), 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017 (pp. 152-153). [7870306] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 60). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2017.7870306

A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. / Coombs, Daniel; Elkholy, Ahmed; Nandwana, Romesh Kumar; Elmallah, Ahmed; Hanumolu, Pavan Kumar.

2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. ed. / Laura C. Fujino. Institute of Electrical and Electronics Engineers Inc., 2017. p. 152-153 7870306 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 60).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Coombs, D, Elkholy, A, Nandwana, RK, Elmallah, A & Hanumolu, PK 2017, A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. in LC Fujino (ed.), 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017., 7870306, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 60, Institute of Electrical and Electronics Engineers Inc., pp. 152-153, 64th IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, United States, 2/5/17. https://doi.org/10.1109/ISSCC.2017.7870306
Coombs D, Elkholy A, Nandwana RK, Elmallah A, Hanumolu PK. A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. In Fujino LC, editor, 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 152-153. 7870306. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2017.7870306
Coombs, Daniel ; Elkholy, Ahmed ; Nandwana, Romesh Kumar ; Elmallah, Ahmed ; Hanumolu, Pavan Kumar. / A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. editor / Laura C. Fujino. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 152-153 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).
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