A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier with Background-Calibrated Reference Frequency Doubler

Ahmed Elkholy; Daniel Coombs; Romesh Kumar Nandwana; Ahmed Elmallah; Pavan Kumar Hanumolu

doi:10.1109/JSSC.2019.2904884

A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier with Background-Calibrated Reference Frequency Doubler

Ahmed Elkholy, Daniel Coombs, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu

Research output: Contribution to journal › Article › peer-review

Abstract

A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented. It employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop (DLL) to achieve second-order suppression of RO noise, and a digital frequency-tracking loop (FTL) to continuously tune the oscillator's free-running frequency and ensure a robust operation across process, voltage, and temperature (PVT) variations. A least-mean-square (LMS) algorithm is used to accurately cancel the deterministic jitter (DJ) caused by input duty cycle errors. Fabricated in the 65-nm CMOS process, the prototype ILCM occupies an active area of 0.09 mm² and generates an output clock in the range of 2.5-5.75 GHz using a 125-MHz reference clock. At 5 GHz, it achieves an integrated jitter of 335 fs_rms, while consuming 5.3 mW of power. This translates to the best reported figure-of-merit (FoM) of -242.4 dB for a ring-based ILCM at this high frequency.

Original language	English (US)
Article number	8691469
Pages (from-to)	2049-2058
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	54
Issue number	7
DOIs	https://doi.org/10.1109/JSSC.2019.2904884
State	Published - Jul 2019

Keywords

Delay line
PLL
delay-locked loop (DLL)
digital phase-locked loop (PLL)
digitally controlled delay line (DCDL)
digitally controlled oscillator (DCO)
flicker noise
frequency doubler
injection locking
injection-locked clock multiplier (ILCM)
jitter
least mean square (LMS)
multiplying injection-locked oscillator (MILO)
phase noise
reference doubler
ring oscillator (RO)

ASJC Scopus subject areas

Electrical and Electronic Engineering

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A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier with Background-Calibrated Reference Frequency Doubler. / Elkholy, Ahmed; Coombs, Daniel; Nandwana, Romesh Kumar; Elmallah, Ahmed; Hanumolu, Pavan Kumar.

In: IEEE Journal of Solid-State Circuits, Vol. 54, No. 7, 8691469, 07.2019, p. 2049-2058.

Research output: Contribution to journal › Article › peer-review

@article{3e7b1bc71487471391d0e1fc77a91289,

title = "A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier with Background-Calibrated Reference Frequency Doubler",

abstract = "A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented. It employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop (DLL) to achieve second-order suppression of RO noise, and a digital frequency-tracking loop (FTL) to continuously tune the oscillator's free-running frequency and ensure a robust operation across process, voltage, and temperature (PVT) variations. A least-mean-square (LMS) algorithm is used to accurately cancel the deterministic jitter (DJ) caused by input duty cycle errors. Fabricated in the 65-nm CMOS process, the prototype ILCM occupies an active area of 0.09 mm2 and generates an output clock in the range of 2.5-5.75 GHz using a 125-MHz reference clock. At 5 GHz, it achieves an integrated jitter of 335 fsrms, while consuming 5.3 mW of power. This translates to the best reported figure-of-merit (FoM) of -242.4 dB for a ring-based ILCM at this high frequency.",

keywords = "Delay line, PLL, delay-locked loop (DLL), digital phase-locked loop (PLL), digitally controlled delay line (DCDL), digitally controlled oscillator (DCO), flicker noise, frequency doubler, injection locking, injection-locked clock multiplier (ILCM), jitter, least mean square (LMS), multiplying injection-locked oscillator (MILO), phase noise, reference doubler, ring oscillator (RO)",

author = "Ahmed Elkholy and Daniel Coombs and Nandwana, {Romesh Kumar} and Ahmed Elmallah and Hanumolu, {Pavan Kumar}",

year = "2019",

month = jul,

doi = "10.1109/JSSC.2019.2904884",

language = "English (US)",

volume = "54",

pages = "2049--2058",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "7",

}

TY - JOUR

T1 - A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier with Background-Calibrated Reference Frequency Doubler

AU - Elkholy, Ahmed

AU - Coombs, Daniel

AU - Nandwana, Romesh Kumar

AU - Elmallah, Ahmed

AU - Hanumolu, Pavan Kumar

PY - 2019/7

Y1 - 2019/7

N2 - A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented. It employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop (DLL) to achieve second-order suppression of RO noise, and a digital frequency-tracking loop (FTL) to continuously tune the oscillator's free-running frequency and ensure a robust operation across process, voltage, and temperature (PVT) variations. A least-mean-square (LMS) algorithm is used to accurately cancel the deterministic jitter (DJ) caused by input duty cycle errors. Fabricated in the 65-nm CMOS process, the prototype ILCM occupies an active area of 0.09 mm2 and generates an output clock in the range of 2.5-5.75 GHz using a 125-MHz reference clock. At 5 GHz, it achieves an integrated jitter of 335 fsrms, while consuming 5.3 mW of power. This translates to the best reported figure-of-merit (FoM) of -242.4 dB for a ring-based ILCM at this high frequency.

AB - A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented. It employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop (DLL) to achieve second-order suppression of RO noise, and a digital frequency-tracking loop (FTL) to continuously tune the oscillator's free-running frequency and ensure a robust operation across process, voltage, and temperature (PVT) variations. A least-mean-square (LMS) algorithm is used to accurately cancel the deterministic jitter (DJ) caused by input duty cycle errors. Fabricated in the 65-nm CMOS process, the prototype ILCM occupies an active area of 0.09 mm2 and generates an output clock in the range of 2.5-5.75 GHz using a 125-MHz reference clock. At 5 GHz, it achieves an integrated jitter of 335 fsrms, while consuming 5.3 mW of power. This translates to the best reported figure-of-merit (FoM) of -242.4 dB for a ring-based ILCM at this high frequency.

KW - Delay line

KW - PLL

KW - delay-locked loop (DLL)

KW - digital phase-locked loop (PLL)

KW - digitally controlled delay line (DCDL)

KW - digitally controlled oscillator (DCO)

KW - flicker noise

KW - frequency doubler

KW - injection locking

KW - injection-locked clock multiplier (ILCM)

KW - jitter

KW - least mean square (LMS)

KW - multiplying injection-locked oscillator (MILO)

KW - phase noise

KW - reference doubler

KW - ring oscillator (RO)

UR - http://www.scopus.com/inward/record.url?scp=85068239463&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85068239463&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2019.2904884

DO - 10.1109/JSSC.2019.2904884

M3 - Article

AN - SCOPUS:85068239463

VL - 54

SP - 2049

EP - 2058

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 7

M1 - 8691469

ER -