Abstract
A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented. It employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop (DLL) to achieve second-order suppression of RO noise, and a digital frequency-tracking loop (FTL) to continuously tune the oscillator's free-running frequency and ensure a robust operation across process, voltage, and temperature (PVT) variations. A least-mean-square (LMS) algorithm is used to accurately cancel the deterministic jitter (DJ) caused by input duty cycle errors. Fabricated in the 65-nm CMOS process, the prototype ILCM occupies an active area of 0.09 mm2 and generates an output clock in the range of 2.5-5.75 GHz using a 125-MHz reference clock. At 5 GHz, it achieves an integrated jitter of 335 fsrms, while consuming 5.3 mW of power. This translates to the best reported figure-of-merit (FoM) of -242.4 dB for a ring-based ILCM at this high frequency.
Original language | English (US) |
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Article number | 8691469 |
Pages (from-to) | 2049-2058 |
Number of pages | 10 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 54 |
Issue number | 7 |
DOIs | |
State | Published - Jul 2019 |
Keywords
- Delay line
- PLL
- delay-locked loop (DLL)
- digital phase-locked loop (PLL)
- digitally controlled delay line (DCDL)
- digitally controlled oscillator (DCO)
- flicker noise
- frequency doubler
- injection locking
- injection-locked clock multiplier (ILCM)
- jitter
- least mean square (LMS)
- multiplying injection-locked oscillator (MILO)
- phase noise
- reference doubler
- ring oscillator (RO)
ASJC Scopus subject areas
- Electrical and Electronic Engineering