TY - JOUR
T1 - A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier with Background-Calibrated Reference Frequency Doubler
AU - Elkholy, Ahmed
AU - Coombs, Daniel
AU - Nandwana, Romesh Kumar
AU - Elmallah, Ahmed
AU - Hanumolu, Pavan Kumar
N1 - Funding Information:
Manuscript received July 19, 2018; revised November 28, 2018; accepted March 1, 2019. Date of publication April 15, 2019; date of current version June 26, 2019. This paper was approved by Associate Editor Azita Emami. This work was supported by Analog Devices. (Corresponding author: Ahmed Elkholy.) A. Elkholy, A. Elmallah, and P. K. Hanumolu are with the Department of Electrical and Computer Engineering, University of Illinois at Urbana– Champaign, Urbana, IL 61801 USA (e-mail: ah.kholy85@gmail.com). D. Coombs is with Ocient Inc., Chicago, IL 60606 USA. R. K. Nandwana is with Cisco Systems, Allentown, PA 18195 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2019.2904884
Publisher Copyright:
© 1966-2012 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented. It employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop (DLL) to achieve second-order suppression of RO noise, and a digital frequency-tracking loop (FTL) to continuously tune the oscillator's free-running frequency and ensure a robust operation across process, voltage, and temperature (PVT) variations. A least-mean-square (LMS) algorithm is used to accurately cancel the deterministic jitter (DJ) caused by input duty cycle errors. Fabricated in the 65-nm CMOS process, the prototype ILCM occupies an active area of 0.09 mm2 and generates an output clock in the range of 2.5-5.75 GHz using a 125-MHz reference clock. At 5 GHz, it achieves an integrated jitter of 335 fsrms, while consuming 5.3 mW of power. This translates to the best reported figure-of-merit (FoM) of -242.4 dB for a ring-based ILCM at this high frequency.
AB - A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented. It employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop (DLL) to achieve second-order suppression of RO noise, and a digital frequency-tracking loop (FTL) to continuously tune the oscillator's free-running frequency and ensure a robust operation across process, voltage, and temperature (PVT) variations. A least-mean-square (LMS) algorithm is used to accurately cancel the deterministic jitter (DJ) caused by input duty cycle errors. Fabricated in the 65-nm CMOS process, the prototype ILCM occupies an active area of 0.09 mm2 and generates an output clock in the range of 2.5-5.75 GHz using a 125-MHz reference clock. At 5 GHz, it achieves an integrated jitter of 335 fsrms, while consuming 5.3 mW of power. This translates to the best reported figure-of-merit (FoM) of -242.4 dB for a ring-based ILCM at this high frequency.
KW - Delay line
KW - PLL
KW - delay-locked loop (DLL)
KW - digital phase-locked loop (PLL)
KW - digitally controlled delay line (DCDL)
KW - digitally controlled oscillator (DCO)
KW - flicker noise
KW - frequency doubler
KW - injection locking
KW - injection-locked clock multiplier (ILCM)
KW - jitter
KW - least mean square (LMS)
KW - multiplying injection-locked oscillator (MILO)
KW - phase noise
KW - reference doubler
KW - ring oscillator (RO)
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U2 - 10.1109/JSSC.2019.2904884
DO - 10.1109/JSSC.2019.2904884
M3 - Article
AN - SCOPUS:85068239463
VL - 54
SP - 2049
EP - 2058
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 7
M1 - 8691469
ER -