A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth

Brian Young, Sunwoo Kwon, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A time-to-digital converter (TDC) employs a phase-reference second-order continuous-time delta-sigma modulator to achieve high resolution and low power. The modulator operates on the phase of the input signal and generates an equivalent noise-shaped one-bit output data stream. Fabricated in an LP 90nm CMOS process, the prototype TDC achieves better than 2.4ps resolution over a 3.2ns range in a 1MHz signal bandwidth while consuming 2.1mW from a 1.2V supply.

Original languageEnglish (US)
Title of host publicationIEEE Custom Integrated Circuits Conference 2010, CICC 2010
DOIs
StatePublished - Dec 13 2010
Externally publishedYes
Event32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 - San Jose, CA, United States
Duration: Sep 19 2010Sep 22 2010

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
CountryUnited States
CitySan Jose, CA
Period9/19/109/22/10

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Young, B., Kwon, S., Elshazly, A., & Hanumolu, P. K. (2010). A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth. In IEEE Custom Integrated Circuits Conference 2010, CICC 2010 [5617612] (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2010.5617612