Abstract
The growth of the Internet as a vehicle for secure communication and electronic commerce has brought cryptographic processing performance to the forefront of high throughput system design. This trend will gain further momentum with the widespread adoption of secure protocols such as secure IP (IPSEC) and virtual private networks (VPNs). In this paper, we present a fully integrated and synthesizable cipher core supporting the Advanced Encryption Standard - Rijndael. We designed and fabricated the fully integrated core - key scheduler, encipher, and decipher using TSMC 0.18μm technology. The core operating frequency is 465MHz and throughput is 2.3Gb/s.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 193-196 |
| Number of pages | 4 |
| Journal | Proceedings of the Custom Integrated Circuits Conference |
| State | Published - Nov 19 2003 |
| Externally published | Yes |
| Event | Proceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, United States Duration: Sep 21 2003 → Sep 24 2003 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering