A 2.3Gb/s fully integrated and synthesizable AES rijndael core

Nam Sung Kim, Trevor Mudge, Richard Brown

Research output: Contribution to journalConference articlepeer-review


The growth of the Internet as a vehicle for secure communication and electronic commerce has brought cryptographic processing performance to the forefront of high throughput system design. This trend will gain further momentum with the widespread adoption of secure protocols such as secure IP (IPSEC) and virtual private networks (VPNs). In this paper, we present a fully integrated and synthesizable cipher core supporting the Advanced Encryption Standard - Rijndael. We designed and fabricated the fully integrated core - key scheduler, encipher, and decipher using TSMC 0.18μm technology. The core operating frequency is 465MHz and throughput is 2.3Gb/s.

Original languageEnglish (US)
Pages (from-to)193-196
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Nov 19 2003
Externally publishedYes
EventProceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, United States
Duration: Sep 21 2003Sep 24 2003

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'A 2.3Gb/s fully integrated and synthesizable AES rijndael core'. Together they form a unique fingerprint.

Cite this