A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL with Extended Range Multi-Modulus Divider

Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Contribution to journalArticlepeer-review


Phase noise performance of ring oscillator based digital fractional-N phase-locked loops (FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the time-to-digital converter (TDC), ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their figure-of-merit (FoMJ) that quantifies the power-jitter tradeoff is at least 25 dB worse than their LC-oscillator-based FNPLL counterparts. This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. Fabricated in 65 nm CMOS process, the proposed FNPLL operates over a wide frequency range of 2.0-5.5 GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9 psrms integrated jitter while consuming only 4 mW at 5 GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1 MHz offset. The proposed FNPLL achieves wide BW up to 6 MHz using a 50 MHz reference and its FoMJ is -228.5 dB, which is the best among all reported ring-based FNPLLs.

Original languageEnglish (US)
Article number7489022
Pages (from-to)1771-1784
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Issue number8
StatePublished - Aug 2016


  • DAC
  • DTC
  • LMS
  • TDC
  • digital PLL
  • digitally controlled oscillator (DCO)
  • dual-path
  • fractional-N
  • frequency synthesizer
  • jitter
  • multi-modulus divider (MMD)
  • phase-locked loops (PLLs)
  • ring oscillator
  • wide bandwidth

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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