A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator

Yongxin Li; Nilanjan Pal; Tianyu Wang; Mostafa Gamal Ahmed; Ahmed Abdelrahman; Mohamed Badr Younis; Kyu Sang Park; Ruhao Xia; Pavan Kumar Hanumolu

doi:10.1109/JSSC.2022.3227139

A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator

Yongxin Li, Nilanjan Pal, Tianyu Wang, Mostafa Gamal Ahmed, Ahmed Abdelrahman, Mohamed Badr Younis, Kyu Sang Park, Ruhao Xia, Pavan Kumar Hanumolu

Research output: Contribution to journal › Article › peer-review

Abstract

A clock generator using a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs) to generate programmable temperature-insensitive output frequencies is presented. Successive approximation register (SAR) logic is used to speed up the locking of the FLL, and truncation error cancellation (TEC) is performed in FDIVs to reduce delta-sigma-induced jitter. A prototype clock generator fabricated in a 65-nm CMOS process generates output clocks in the range of 1.5-100 MHz with a resolution of 24-kHz, 140-ps peak-to-peak period jitter, 6.8-ppm/°C inaccuracy, and can be turned on within 20 μs.

Original language	English (US)
Pages (from-to)	785-795
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	58
Issue number	3
DOIs	https://doi.org/10.1109/JSSC.2022.3227139
State	Published - Mar 1 2023

Keywords

Delta-sigma modulator
RC oscillator
fractional divider (FDIV)
frequency-locked loop (FLL)
phase-locked loop (PLL)
ring voltage-controlled oscillator (VCO)
temperature compensation

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/JSSC.2022.3227139

Library availability

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title = "A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator",

abstract = "A clock generator using a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs) to generate programmable temperature-insensitive output frequencies is presented. Successive approximation register (SAR) logic is used to speed up the locking of the FLL, and truncation error cancellation (TEC) is performed in FDIVs to reduce delta-sigma-induced jitter. A prototype clock generator fabricated in a 65-nm CMOS process generates output clocks in the range of 1.5-100 MHz with a resolution of 24-kHz, 140-ps peak-to-peak period jitter, 6.8-ppm/°C inaccuracy, and can be turned on within 20 μs.",

keywords = "Delta-sigma modulator, RC oscillator, fractional divider (FDIV), frequency-locked loop (FLL), phase-locked loop (PLL), ring voltage-controlled oscillator (VCO), temperature compensation",

author = "Yongxin Li and Nilanjan Pal and Tianyu Wang and {Gamal Ahmed}, Mostafa and Ahmed Abdelrahman and {Badr Younis}, Mohamed and Park, {Kyu Sang} and Ruhao Xia and Hanumolu, {Pavan Kumar}",

note = "Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

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doi = "10.1109/JSSC.2022.3227139",

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AU - Li, Yongxin

AU - Pal, Nilanjan

AU - Wang, Tianyu

AU - Gamal Ahmed, Mostafa

AU - Abdelrahman, Ahmed

AU - Badr Younis, Mohamed

AU - Park, Kyu Sang

AU - Xia, Ruhao

AU - Hanumolu, Pavan Kumar

PY - 2023/3/1

Y1 - 2023/3/1

N2 - A clock generator using a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs) to generate programmable temperature-insensitive output frequencies is presented. Successive approximation register (SAR) logic is used to speed up the locking of the FLL, and truncation error cancellation (TEC) is performed in FDIVs to reduce delta-sigma-induced jitter. A prototype clock generator fabricated in a 65-nm CMOS process generates output clocks in the range of 1.5-100 MHz with a resolution of 24-kHz, 140-ps peak-to-peak period jitter, 6.8-ppm/°C inaccuracy, and can be turned on within 20 μs.

AB - A clock generator using a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs) to generate programmable temperature-insensitive output frequencies is presented. Successive approximation register (SAR) logic is used to speed up the locking of the FLL, and truncation error cancellation (TEC) is performed in FDIVs to reduce delta-sigma-induced jitter. A prototype clock generator fabricated in a 65-nm CMOS process generates output clocks in the range of 1.5-100 MHz with a resolution of 24-kHz, 140-ps peak-to-peak period jitter, 6.8-ppm/°C inaccuracy, and can be turned on within 20 μs.

KW - Delta-sigma modulator

KW - RC oscillator

KW - fractional divider (FDIV)

KW - frequency-locked loop (FLL)

KW - phase-locked loop (PLL)

KW - ring voltage-controlled oscillator (VCO)

KW - temperature compensation

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A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator

Abstract

Keywords

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