TY - GEN
T1 - A 20μs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy
AU - Li, Yongxin
AU - Pal, Nilanjan
AU - Wang, Tianyu
AU - Ahmed, Mostafa Gamal
AU - Abdelrahman, Ahmed
AU - Younis, Mohamed Badr
AU - Xia, Ruhao
AU - Park, Kyu Sang
AU - Kumar Hanumolu, Pavan
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The demand for portable electronic devices with a small form factor and extended battery life is ever increasing. Timing circuits impose several critical impediments in meeting this demand. For example, low-power microcontroller units use multiple crystal oscillators (XOs) and several on-chip fractional-N phase-locked loops (PLLs) to generate the desired clocks, which significantly increase board space, power consumption. XOs and PLLs cannot be turned ON and OFF rapidly, so they also severely limit the ability to employ system-level power-reduction strategies such as power cycling. On-chip closed-loop frequency-locked loop (FLL) based oscillators are promising candidates to address some of these drawbacks [1]. While they can achieve excellent frequency accuracy, they occupy a large area, consume significant power, and cannot be turned ON/OFF rapidly due to their very low bandwidth and can only provide an output at one fixed frequency. Given these drawbacks, this paper presents a fast start-up, temperature-stable digital FLL-based oscillator and low jitter open-loop fractional dividers that can provide highly programmable clock outputs. Fabricated in a 65nm CMOS process, the prototype can generate clock outputs from about 1.5MHz to 100MHz with a frequency inaccuracy and resolution of 7.5ppm/°C and 24kHz, respectively.
AB - The demand for portable electronic devices with a small form factor and extended battery life is ever increasing. Timing circuits impose several critical impediments in meeting this demand. For example, low-power microcontroller units use multiple crystal oscillators (XOs) and several on-chip fractional-N phase-locked loops (PLLs) to generate the desired clocks, which significantly increase board space, power consumption. XOs and PLLs cannot be turned ON and OFF rapidly, so they also severely limit the ability to employ system-level power-reduction strategies such as power cycling. On-chip closed-loop frequency-locked loop (FLL) based oscillators are promising candidates to address some of these drawbacks [1]. While they can achieve excellent frequency accuracy, they occupy a large area, consume significant power, and cannot be turned ON/OFF rapidly due to their very low bandwidth and can only provide an output at one fixed frequency. Given these drawbacks, this paper presents a fast start-up, temperature-stable digital FLL-based oscillator and low jitter open-loop fractional dividers that can provide highly programmable clock outputs. Fabricated in a 65nm CMOS process, the prototype can generate clock outputs from about 1.5MHz to 100MHz with a frequency inaccuracy and resolution of 7.5ppm/°C and 24kHz, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85130747532&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85130747532&partnerID=8YFLogxK
U2 - 10.1109/CICC53496.2022.9772819
DO - 10.1109/CICC53496.2022.9772819
M3 - Conference contribution
AN - SCOPUS:85130747532
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - 2022 IEEE Custom Integrated Circuits Conference, CICC 2022 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 43rd Annual IEEE Custom Integrated Circuits Conference, CICC 2022
Y2 - 24 April 2022 through 27 April 2022
ER -