This paper describes a downconversion filter which uses variable delay clocks to simultaneously perform downconversion mixing and filter bandwidth tuning. This method of bandwidth tuning is highly linear and applicable to low supply voltages. The test chip fabricated in a 0.18μm CMOS process achieves 19.2dBV IIP3 at IV and has a bandwidth that is tunable over a ±50% range. The downconversion filter mixes and filters an 830MHz Input to a nominal 300kHz bandwidth at DC.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 2008|
ASJC Scopus subject areas
- Electrical and Electronic Engineering