A 1V downconversion filter using duty-cycle controlled bandwidth tuning

Peter Kurahashi, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Contribution to journalArticle

Abstract

This paper describes a downconversion filter which uses variable delay clocks to simultaneously perform downconversion mixing and filter bandwidth tuning. This method of bandwidth tuning is highly linear and applicable to low supply voltages. The test chip fabricated in a 0.18μm CMOS process achieves 19.2dBV IIP3 at IV and has a bandwidth that is tunable over a ±50% range. The downconversion filter mixes and filters an 830MHz Input to a nominal 300kHz bandwidth at DC.

Original languageEnglish (US)
Article number4672185
Pages (from-to)707-710
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 2008
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 1V downconversion filter using duty-cycle controlled bandwidth tuning'. Together they form a unique fingerprint.

  • Cite this