A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array

Mingu Kang, Sujan K. Gonugondla, Naresh R. Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents IC realization of a random forest (RF) machine learning classifier. Algorithm-architecture-circuit is co-optimized to minimize the energy-delay product (EDP). Deterministic subsampling (DSS) and balanced decision trees result in reduced interconnect complexity and avoid irregular memory accesses. Low-swing analog in-memory computations embedded in a standard 6T SRAM enable massively parallel processing thereby minimizing the memory fetches and reducing the EDP further. The 65nm CMOS prototype achieves a 6.8× lower EDP compared to a conventional design at the same accuracy (94%) for an 8-class traffic sign recognition problem.

Original languageEnglish (US)
Title of host publicationESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages263-266
Number of pages4
ISBN (Electronic)9781509050253
DOIs
StatePublished - Nov 2 2017
Event43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017 - Leuven, Belgium
Duration: Sep 11 2017Sep 14 2017

Publication series

NameESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference

Other

Other43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017
CountryBelgium
CityLeuven
Period9/11/179/14/17

Keywords

  • In-memory computing
  • Machine learning
  • Pattern recognition
  • Random forest
  • Traffic sign recognition

ASJC Scopus subject areas

  • Instrumentation
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Computer Networks and Communications

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