A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing

Naga Sasidhar; Youn Jae Kook; Seiji Takeuchi; Koichi Hamashita; Kaoru Takasuka; Pavan Kumar Hanumolu; Un Ku Moon

doi:10.1109/ASSCC.2007.4425775

A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing

Naga Sasidhar, Youn Jae Kook, Seiji Takeuchi, Koichi Hamashita, Kaoru Takasuka, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A new capacitor and opamp sharing technique that enables a very efficient low power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back in the absence of sample and hold is also presented. Fabricated in a 0.18-μm CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm² of active die area and achieves 66.7dB SFDR and 53.2dB SNDR when a 1MHz input signal is digitized at 80MS/s. The SFDR and SNDR are unchanged for 50MHz input signal. The prototype ADC consumes 36mW at 1.8V supply, of which analog portion consumes 24mW.

Original language	English (US)
Title of host publication	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages	240-243
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2007.4425775
State	Published - 2007
Externally published	Yes
Event	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of Duration: Nov 12 2007 → Nov 14 2007

Publication series

Name	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Other

Other	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Country/Territory	Korea, Republic of
City	Jeju
Period	11/12/07 → 11/14/07

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Online availability

10.1109/ASSCC.2007.4425775

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Sasidhar, N., Kook, Y. J., Takeuchi, S., Hamashita, K., Takasuka, K., Hanumolu, P. K., & Moon, U. K. (2007). A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing. In 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC (pp. 240-243). Article 4425775 (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC). https://doi.org/10.1109/ASSCC.2007.4425775

Sasidhar, N, Kook, YJ, Takeuchi, S, Hamashita, K, Takasuka, K, Hanumolu, PK & Moon, UK 2007, A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing. in 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC., 4425775, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp. 240-243, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, Jeju, Korea, Republic of, 11/12/07. https://doi.org/10.1109/ASSCC.2007.4425775

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abstract = "A new capacitor and opamp sharing technique that enables a very efficient low power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back in the absence of sample and hold is also presented. Fabricated in a 0.18-μm CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm2 of active die area and achieves 66.7dB SFDR and 53.2dB SNDR when a 1MHz input signal is digitized at 80MS/s. The SFDR and SNDR are unchanged for 50MHz input signal. The prototype ADC consumes 36mW at 1.8V supply, of which analog portion consumes 24mW.",

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AU - Takasuka, Kaoru

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AB - A new capacitor and opamp sharing technique that enables a very efficient low power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back in the absence of sample and hold is also presented. Fabricated in a 0.18-μm CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm2 of active die area and achieves 66.7dB SFDR and 53.2dB SNDR when a 1MHz input signal is digitized at 80MS/s. The SFDR and SNDR are unchanged for 50MHz input signal. The prototype ADC consumes 36mW at 1.8V supply, of which analog portion consumes 24mW.

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A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing

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