@inproceedings{0e3df19e4ab645d7891c670c04df85b8,
title = "A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS",
abstract = "A wide range high resolution 2-stage digital-to-time converter (DTC) is presented. It uses a counter in the first stage and a digitally controlled delay line in the second stage to decouple the range versus resolution trade-off. Background calibration is used to correct interstage gain error. Fabricated in 65nm, the prototype DTC achieves 1.65ps-peak-integral non-linearity (INL) while consuming 10.13mW at 100MHz carrier frequency. The achieved dynamic range is 15dB higher than state-of-the-art DTCs.",
keywords = "DCDL, DTC, INL, background calibration, phase noise, segmentation",
author = "Ahmed Elmallah and Ahmed, {Mostafa Gamal} and Ahmed Elkholy and Choi, {Woo Seok} and Hanumolu, {Pavan Kumar}",
note = "Funding Information: VII. ACKNOWLEDGMENT This work was supported in part by Systems on Nanoscale Information fabriCs (SONIC), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA. We thank Mentor Graphics for providing Analog Fast Spice (AFS) simulator. Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 ; Conference date: 08-04-2018 Through 11-04-2018",
year = "2018",
month = may,
day = "9",
doi = "10.1109/CICC.2018.8357042",
language = "English (US)",
series = "2018 IEEE Custom Integrated Circuits Conference, CICC 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--4",
booktitle = "2018 IEEE Custom Integrated Circuits Conference, CICC 2018",
address = "United States",
}