A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS

Ahmed Elmallah, Mostafa Gamal Ahmed, Ahmed Elkholy, Woo Seok Choi, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A wide range high resolution 2-stage digital-to-time converter (DTC) is presented. It uses a counter in the first stage and a digitally controlled delay line in the second stage to decouple the range versus resolution trade-off. Background calibration is used to correct interstage gain error. Fabricated in 65nm, the prototype DTC achieves 1.65ps-peak-integral non-linearity (INL) while consuming 10.13mW at 100MHz carrier frequency. The achieved dynamic range is 15dB higher than state-of-the-art DTCs.

Original languageEnglish (US)
Title of host publication2018 IEEE Custom Integrated Circuits Conference, CICC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538624838
DOIs
StatePublished - May 9 2018
Event2018 IEEE Custom Integrated Circuits Conference, CICC 2018 - San Diego, United States
Duration: Apr 8 2018Apr 11 2018

Publication series

Name2018 IEEE Custom Integrated Circuits Conference, CICC 2018

Other

Other2018 IEEE Custom Integrated Circuits Conference, CICC 2018
CountryUnited States
CitySan Diego
Period4/8/184/11/18

Keywords

  • DCDL
  • DTC
  • INL
  • background calibration
  • phase noise
  • segmentation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Elmallah, A., Ahmed, M. G., Elkholy, A., Choi, W. S., & Hanumolu, P. K. (2018). A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS. In 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 (pp. 1-4). (2018 IEEE Custom Integrated Circuits Conference, CICC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2018.8357042