A 1.6mW 1.6ps-rms-Jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS

Wenjing Yin, Rajesh Inti, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A digital phase-locked loop (DPLL) employs a linear proportional path, a double integral path, bandwidth and tuning range tracking, and a novel delta-sigma digital to analog converter to achieve low jitter, wide operating range and low power. The prototype DPLL fabricated in a 90nm CMOS process operates from 0.7 to 3.5GHz. At 2.5GHz, the proposed DPLL consumes only 1.6mW power from a 1V supply and achieves 1.6ps and 11.6ps of long-term r.m.s and peak-to-peak jitter, respectively.

Original languageEnglish (US)
Title of host publicationIEEE Custom Integrated Circuits Conference 2010, CICC 2010
DOIs
StatePublished - Dec 13 2010
Externally publishedYes
Event32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 - San Jose, CA, United States
Duration: Sep 19 2010Sep 22 2010

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
CountryUnited States
CitySan Jose, CA
Period9/19/109/22/10

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Yin, W., Inti, R., & Hanumolu, P. K. (2010). A 1.6mW 1.6ps-rms-Jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS. In IEEE Custom Integrated Circuits Conference 2010, CICC 2010 [5617611] (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2010.5617611