TY - GEN
T1 - A 1.6mW 1.6ps-rms-Jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS
AU - Yin, Wenjing
AU - Inti, Rajesh
AU - Hanumolu, Pavan Kumar
PY - 2010/12/13
Y1 - 2010/12/13
N2 - A digital phase-locked loop (DPLL) employs a linear proportional path, a double integral path, bandwidth and tuning range tracking, and a novel delta-sigma digital to analog converter to achieve low jitter, wide operating range and low power. The prototype DPLL fabricated in a 90nm CMOS process operates from 0.7 to 3.5GHz. At 2.5GHz, the proposed DPLL consumes only 1.6mW power from a 1V supply and achieves 1.6ps and 11.6ps of long-term r.m.s and peak-to-peak jitter, respectively.
AB - A digital phase-locked loop (DPLL) employs a linear proportional path, a double integral path, bandwidth and tuning range tracking, and a novel delta-sigma digital to analog converter to achieve low jitter, wide operating range and low power. The prototype DPLL fabricated in a 90nm CMOS process operates from 0.7 to 3.5GHz. At 2.5GHz, the proposed DPLL consumes only 1.6mW power from a 1V supply and achieves 1.6ps and 11.6ps of long-term r.m.s and peak-to-peak jitter, respectively.
UR - http://www.scopus.com/inward/record.url?scp=78649810897&partnerID=8YFLogxK
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U2 - 10.1109/CICC.2010.5617611
DO - 10.1109/CICC.2010.5617611
M3 - Conference contribution
AN - SCOPUS:78649810897
SN - 9781424457588
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - IEEE Custom Integrated Circuits Conference 2010, CICC 2010
T2 - 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
Y2 - 19 September 2010 through 22 September 2010
ER -