A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS

Dynamic voltage and frequency scaling (DVFS) [1] and burst-mode operation [2] are two promising methods to greatly improve energy efficiency of serial links. By varying supply voltage in accordance with the desired data rate/workload, DVFS scales link power almost quadratically with data rate. Because the time constant associated with changing the output of a DC-DC converter that provides the optimal link supply voltage is on the order of several microseconds, DVFS is effective only when rate of workload variations is slow. On the other hand, burst-mode communication, implemented using rapid on/off (ROO) links, linearly scales power consumption with effective data rate and is well-suited for interfaces where link inactive periods are short, on the order of few hundred nano-seconds or less. However, energy efficiency of ROO links degrades considerably at lower utilization levels due to leakage and static power consumed in the off state. Hence, DVFS and ROO techniques are best suited for workload variations with large and small time constants, respectively. In practice, their effectiveness also greatly depends on the integrity of supply voltage as it is stressed considerably more compared to always-on links operating at a fixed supply voltage. In this paper, we seek to combine DVFS and ROO approaches along with robust supply voltage generation and regulation techniques to achieve excellent energy efficiency across a wide range of data rates. The prototype source synchronous transceiver is implemented in a 65nm CMOS process and is packaged in a 10mm×10mm QFN package. It achieves less than 14ns wake-up time with 14.1-5.9pJ/b energy efficiency for the effective data rates varying from 16Mb/s to 8Gb/s.