A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS

Guanghua Shu, Woo Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Dynamic voltage and frequency scaling (DVFS) [1] and burst-mode operation [2] are two promising methods to greatly improve energy efficiency of serial links. By varying supply voltage in accordance with the desired data rate/workload, DVFS scales link power almost quadratically with data rate. Because the time constant associated with changing the output of a DC-DC converter that provides the optimal link supply voltage is on the order of several microseconds, DVFS is effective only when rate of workload variations is slow. On the other hand, burst-mode communication, implemented using rapid on/off (ROO) links, linearly scales power consumption with effective data rate and is well-suited for interfaces where link inactive periods are short, on the order of few hundred nano-seconds or less. However, energy efficiency of ROO links degrades considerably at lower utilization levels due to leakage and static power consumed in the off state. Hence, DVFS and ROO techniques are best suited for workload variations with large and small time constants, respectively. In practice, their effectiveness also greatly depends on the integrity of supply voltage as it is stressed considerably more compared to always-on links operating at a fixed supply voltage. In this paper, we seek to combine DVFS and ROO approaches along with robust supply voltage generation and regulation techniques to achieve excellent energy efficiency across a wide range of data rates. The prototype source synchronous transceiver is implemented in a 65nm CMOS process and is packaged in a 10mm×10mm QFN package. It achieves less than 14ns wake-up time with 14.1-5.9pJ/b energy efficiency for the effective data rates varying from 16Mb/s to 8Gb/s.

Original languageEnglish (US)
Title of host publication2016 IEEE International Solid-State Circuits Conference, ISSCC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages398-399
Number of pages2
ISBN (Electronic)9781467394666
DOIs
StatePublished - Feb 23 2016
Event63rd IEEE International Solid-State Circuits Conference, ISSCC 2016 - San Francisco, United States
Duration: Jan 31 2016Feb 4 2016

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume59
ISSN (Print)0193-6530

Other

Other63rd IEEE International Solid-State Circuits Conference, ISSCC 2016
CountryUnited States
CitySan Francisco
Period1/31/162/4/16

Fingerprint

Transceivers
Energy efficiency
Electric potential
DC-DC converters
Electric power utilization
Voltage scaling
Dynamic frequency scaling
Communication

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Shu, G., Choi, W. S., Saxena, S., Kim, S. J., Talegaonkar, M., Nandwana, R., ... Hanumolu, P. K. (2016). A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016 (pp. 398-399). [7418075] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 59). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2016.7418075

A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. / Shu, Guanghua; Choi, Woo Seok; Saxena, Saurabh; Kim, Seong Joong; Talegaonkar, Mrunmay; Nandwana, Romesh; Elkholy, Ahmed; Wei, Da; Nandi, Timir; Hanumolu, Pavan Kumar.

2016 IEEE International Solid-State Circuits Conference, ISSCC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 398-399 7418075 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 59).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shu, G, Choi, WS, Saxena, S, Kim, SJ, Talegaonkar, M, Nandwana, R, Elkholy, A, Wei, D, Nandi, T & Hanumolu, PK 2016, A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. in 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016., 7418075, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 59, Institute of Electrical and Electronics Engineers Inc., pp. 398-399, 63rd IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, United States, 1/31/16. https://doi.org/10.1109/ISSCC.2016.7418075
Shu G, Choi WS, Saxena S, Kim SJ, Talegaonkar M, Nandwana R et al. A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 398-399. 7418075. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2016.7418075
Shu, Guanghua ; Choi, Woo Seok ; Saxena, Saurabh ; Kim, Seong Joong ; Talegaonkar, Mrunmay ; Nandwana, Romesh ; Elkholy, Ahmed ; Wei, Da ; Nandi, Timir ; Hanumolu, Pavan Kumar. / A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 398-399 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).
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