A 1.6Gbps digital clock and data recovery circuit

Pavan Kumar Hanumolu, Min Gyu Kim, Gu Yeon Wei, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A digital clock and data recovery circuit employs simple 3-level digital-to-analog converters to interface the digital loop Alter to the voltage controlled oscillator and achieves low jitter performance. Test chip fabricated in a 0.13μm CMOS process achieves BER < 10-12, ±1500ppm lock-in range, ±2500ppm tracking range, recovered clock Jitter of 8.9ps rms and consumes 12mW power from a single-pin 1.2V supply, while operating at 1.6Gbps.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Pages603-606
Number of pages4
DOIs
StatePublished - Dec 1 2006
Externally publishedYes
EventIEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States
Duration: Sep 10 2006Sep 13 2006

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

OtherIEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Country/TerritoryUnited States
CitySan Jose, CA
Period9/10/069/13/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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