A 1.6Gbps digital clock and data recovery circuit

Pavan Kumar Hanumolu; Min Gyu Kim; Gu Yeon Wei; Un Ku Moon

doi:10.1109/CICC.2006.320829

A 1.6Gbps digital clock and data recovery circuit

Pavan Kumar Hanumolu, Min Gyu Kim, Gu Yeon Wei, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A digital clock and data recovery circuit employs simple 3-level digital-to-analog converters to interface the digital loop Alter to the voltage controlled oscillator and achieves low jitter performance. Test chip fabricated in a 0.13μm CMOS process achieves BER < 10^-12, ±1500ppm lock-in range, ±2500ppm tracking range, recovered clock Jitter of 8.9ps rms and consumes 12mW power from a single-pin 1.2V supply, while operating at 1.6Gbps.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Pages	603-606
Number of pages	4
DOIs	https://doi.org/10.1109/CICC.2006.320829
State	Published - 2006
Externally published	Yes
Event	IEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States Duration: Sep 10 2006 → Sep 13 2006

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Country/Territory	United States
City	San Jose, CA
Period	9/10/06 → 9/13/06

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/CICC.2006.320829

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Hanumolu, PK, Kim, MG, Wei, GY & Moon, UK 2006, A 1.6Gbps digital clock and data recovery circuit. in Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006., 4115031, Proceedings of the Custom Integrated Circuits Conference, pp. 603-606, IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, San Jose, CA, United States, 9/10/06. https://doi.org/10.1109/CICC.2006.320829

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AB - A digital clock and data recovery circuit employs simple 3-level digital-to-analog converters to interface the digital loop Alter to the voltage controlled oscillator and achieves low jitter performance. Test chip fabricated in a 0.13μm CMOS process achieves BER < 10-12, ±1500ppm lock-in range, ±2500ppm tracking range, recovered clock Jitter of 8.9ps rms and consumes 12mW power from a single-pin 1.2V supply, while operating at 1.6Gbps.

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A 1.6Gbps digital clock and data recovery circuit

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