TY - JOUR
T1 - A 16-mW 78-dB SNDR 10-MHz BW CT Δσ ADC Using Residue-Cancelling VCO-Based Quantizer
AU - Reddy, Karthikeyan
AU - Rao, Sachin
AU - Inti, Rajesh
AU - Young, Brian
AU - Elshazly, Amr
AU - Talegaonkar, Mrunmay
AU - Hanumolu, Pavan Kumar
N1 - Funding Information:
Manuscript received April 15, 2012; revised July 12, 2012; accepted August 13, 2012. Date of publication October 23, 2012; date of current version December 21, 2012. This paper was approved by Guest Editor Marco Corsi. This work was supported in part by CESIGN Inc., Korea. K. Reddy, S. Rao, B. Young, M. Talegaonkar, and P. K. Hanumolu are with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331 USA. R. Inti is with Intel Corporation, Hillsboro, OR 97124 USA. A. Elshazly was with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331 USA. He is now with Intel Corporation, Hillsboro, OR 97124 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2012.2218062
PY - 2012
Y1 - 2012
N2 - This paper presents a continuous-time (CT) Δσ modulator using a VCO-based internal quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue canceling quantizer (RCQ) and mitigates the impact of its nonlinearity by spanning only a small region of the VCO's V-to-F nonlinear tuning curve. The order of noise shaping is increased by placing the RCQ in a continuous-time Δσ loop. Using only a first order loop filter, the proposed Δσ modulator achieves second order noise shaping. Fabricated in a 90-nm CMOS process, the prototype modulator occupies an active area of 0.36 mm2 and consumes 16 mW power. It achieves a peak SNDR of 78.3 dB in 10-MHz bandwidth and an SFDR of better than 85 dB when clocked at 600 MHz. The figure of merit of the modulator is 120 fJ/conv-step.
AB - This paper presents a continuous-time (CT) Δσ modulator using a VCO-based internal quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue canceling quantizer (RCQ) and mitigates the impact of its nonlinearity by spanning only a small region of the VCO's V-to-F nonlinear tuning curve. The order of noise shaping is increased by placing the RCQ in a continuous-time Δσ loop. Using only a first order loop filter, the proposed Δσ modulator achieves second order noise shaping. Fabricated in a 90-nm CMOS process, the prototype modulator occupies an active area of 0.36 mm2 and consumes 16 mW power. It achieves a peak SNDR of 78.3 dB in 10-MHz bandwidth and an SFDR of better than 85 dB when clocked at 600 MHz. The figure of merit of the modulator is 120 fJ/conv-step.
KW - Continuous time Δσ modulators
KW - VCO-based ADCs
KW - residue canceling quantizers (RCQs)
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U2 - 10.1109/JSSC.2012.2218062
DO - 10.1109/JSSC.2012.2218062
M3 - Article
AN - SCOPUS:84871800367
SN - 0018-9200
VL - 47
SP - 2916
EP - 2927
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 12
M1 - 6338303
ER -