A 16-mW 78-dB SNDR 10-MHz BW CT Δσ ADC Using Residue-Cancelling VCO-Based Quantizer

Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu

Research output: Contribution to journalArticlepeer-review


This paper presents a continuous-time (CT) Δσ modulator using a VCO-based internal quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue canceling quantizer (RCQ) and mitigates the impact of its nonlinearity by spanning only a small region of the VCO's V-to-F nonlinear tuning curve. The order of noise shaping is increased by placing the RCQ in a continuous-time Δσ loop. Using only a first order loop filter, the proposed Δσ modulator achieves second order noise shaping. Fabricated in a 90-nm CMOS process, the prototype modulator occupies an active area of 0.36 mm2 and consumes 16 mW power. It achieves a peak SNDR of 78.3 dB in 10-MHz bandwidth and an SFDR of better than 85 dB when clocked at 600 MHz. The figure of merit of the modulator is 120 fJ/conv-step.

Original languageEnglish (US)
Article number6338303
Pages (from-to)2916-2927
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Issue number12
StatePublished - 2012
Externally publishedYes


  • Continuous time Δσ modulators
  • VCO-based ADCs
  • residue canceling quantizers (RCQs)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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