TY - GEN
T1 - A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity
AU - Elshazly, Amr
AU - Inti, Rajesh
AU - Talegaonkar, Mrunmay
AU - Hanumolu, Pavan Kumar
PY - 2012/9/28
Y1 - 2012/9/28
N2 - A highly digital PLL employs a 1b TDC and a low power regulator to reduce output jitter in the presence of large amount of supply-noise. Fabricated in a 0.13μm CMOS process, the ring-oscillator based DPLL consumes 1.35mW at 1.5GHz output frequency and achieves better than 50fs/mV worst-case noise sensitivity (≡10ps pp jitter degradation with 200mV pp noise).
AB - A highly digital PLL employs a 1b TDC and a low power regulator to reduce output jitter in the presence of large amount of supply-noise. Fabricated in a 0.13μm CMOS process, the ring-oscillator based DPLL consumes 1.35mW at 1.5GHz output frequency and achieves better than 50fs/mV worst-case noise sensitivity (≡10ps pp jitter degradation with 200mV pp noise).
UR - http://www.scopus.com/inward/record.url?scp=84866611144&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84866611144&partnerID=8YFLogxK
U2 - 10.1109/VLSIC.2012.6243853
DO - 10.1109/VLSIC.2012.6243853
M3 - Conference contribution
AN - SCOPUS:84866611144
SN - 9781467308458
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 188
EP - 189
BT - 2012 Symposium on VLSI Circuits, VLSIC 2012
T2 - 2012 Symposium on VLSI Circuits, VLSIC 2012
Y2 - 13 June 2012 through 15 June 2012
ER -