A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity

Amr Elshazly, Rajesh Inti, Mrunmay Talegaonkar, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A highly digital PLL employs a 1b TDC and a low power regulator to reduce output jitter in the presence of large amount of supply-noise. Fabricated in a 0.13μm CMOS process, the ring-oscillator based DPLL consumes 1.35mW at 1.5GHz output frequency and achieves better than 50fs/mV worst-case noise sensitivity (≡10ps pp jitter degradation with 200mV pp noise).

Original languageEnglish (US)
Title of host publication2012 Symposium on VLSI Circuits, VLSIC 2012
Pages188-189
Number of pages2
DOIs
StatePublished - Sep 28 2012
Externally publishedYes
Event2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States
Duration: Jun 13 2012Jun 15 2012

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2012 Symposium on VLSI Circuits, VLSIC 2012
CountryUnited States
CityHonolulu, HI
Period6/13/126/15/12

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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