A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity

Amr Elshazly; Rajesh Inti; Mrunmay Talegaonkar; Pavan Kumar Hanumolu

doi:10.1109/VLSIC.2012.6243853

A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity

Amr Elshazly, Rajesh Inti, Mrunmay Talegaonkar, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A highly digital PLL employs a 1b TDC and a low power regulator to reduce output jitter in the presence of large amount of supply-noise. Fabricated in a 0.13μm CMOS process, the ring-oscillator based DPLL consumes 1.35mW at 1.5GHz output frequency and achieves better than 50fs/mV worst-case noise sensitivity (≡10ps _pp jitter degradation with 200mV _pp noise).

Original language	English (US)
Title of host publication	2012 Symposium on VLSI Circuits, VLSIC 2012
Pages	188-189
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2012.6243853
State	Published - 2012
Externally published	Yes
Event	2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States Duration: Jun 13 2012 → Jun 15 2012

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2012 Symposium on VLSI Circuits, VLSIC 2012
Country/Territory	United States
City	Honolulu, HI
Period	6/13/12 → 6/15/12

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Online availability

10.1109/VLSIC.2012.6243853

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A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity. / Elshazly, Amr; Inti, Rajesh; Talegaonkar, Mrunmay et al.
2012 Symposium on VLSI Circuits, VLSIC 2012. 2012. p. 188-189 6243853 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Elshazly, A, Inti, R, Talegaonkar, M & Hanumolu, PK 2012, A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity. in 2012 Symposium on VLSI Circuits, VLSIC 2012., 6243853, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 188-189, 2012 Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, United States, 6/13/12. https://doi.org/10.1109/VLSIC.2012.6243853

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abstract = "A highly digital PLL employs a 1b TDC and a low power regulator to reduce output jitter in the presence of large amount of supply-noise. Fabricated in a 0.13μm CMOS process, the ring-oscillator based DPLL consumes 1.35mW at 1.5GHz output frequency and achieves better than 50fs/mV worst-case noise sensitivity (≡10ps pp jitter degradation with 200mV pp noise).",

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year = "2012",

doi = "10.1109/VLSIC.2012.6243853",

language = "English (US)",

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A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity

Abstract

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