A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR

Dongwook Kim, Woo Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


A sub-baud-rate CDR that can recover clock and data using only a quarter-rate clock is presented. Four data bits are recovered in each clock cycle using eight samplers and a current integrator. Four of the eight samplers used for data recovery are re-used for phase detection. Fabricated in a 65nm CMOS process and operating with 11dB channel loss, the prototype CDR recovers 15.2Gb/s data using a 3.8GHz clock and achieves BER < 10-12, > 10MHz JTOL corner, 548fsrms recovered clock jitter, and 1.9pJ/bit energy efficiency.

Original languageEnglish (US)
Title of host publication2018 IEEE Custom Integrated Circuits Conference, CICC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)9781538624838
StatePublished - May 9 2018
Event2018 IEEE Custom Integrated Circuits Conference, CICC 2018 - San Diego, United States
Duration: Apr 8 2018Apr 11 2018

Publication series

Name2018 IEEE Custom Integrated Circuits Conference, CICC 2018


Other2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Country/TerritoryUnited States
CitySan Diego


  • 2x oversampling
  • Clock and data recovery (CDR)
  • baud-rate
  • current integrator
  • sub-baud-rate

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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