A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR

Dongwook Kim, Woo Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A sub-baud-rate CDR that can recover clock and data using only a quarter-rate clock is presented. Four data bits are recovered in each clock cycle using eight samplers and a current integrator. Four of the eight samplers used for data recovery are re-used for phase detection. Fabricated in a 65nm CMOS process and operating with 11dB channel loss, the prototype CDR recovers 15.2Gb/s data using a 3.8GHz clock and achieves BER < 10-12, > 10MHz JTOL corner, 548fsrms recovered clock jitter, and 1.9pJ/bit energy efficiency.

Original languageEnglish (US)
Title of host publication2018 IEEE Custom Integrated Circuits Conference, CICC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538624838
DOIs
StatePublished - May 9 2018
Event2018 IEEE Custom Integrated Circuits Conference, CICC 2018 - San Diego, United States
Duration: Apr 8 2018Apr 11 2018

Other

Other2018 IEEE Custom Integrated Circuits Conference, CICC 2018
CountryUnited States
CitySan Diego
Period4/8/184/11/18

Fingerprint

Clocks
Jitter
Energy efficiency
Recovery

Keywords

  • 2x oversampling
  • baud-rate
  • Clock and data recovery (CDR)
  • current integrator
  • sub-baud-rate

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kim, D., Choi, W. S., Elkholy, A., Kenney, J., & Hanumolu, P. K. (2018). A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. In 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 (pp. 1-4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2018.8357078

A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. / Kim, Dongwook; Choi, Woo Seok; Elkholy, Ahmed; Kenney, Jack; Hanumolu, Pavan Kumar.

2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, D, Choi, WS, Elkholy, A, Kenney, J & Hanumolu, PK 2018, A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. in 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, United States, 4/8/18. https://doi.org/10.1109/CICC.2018.8357078
Kim D, Choi WS, Elkholy A, Kenney J, Hanumolu PK. A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. In 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4 https://doi.org/10.1109/CICC.2018.8357078
Kim, Dongwook ; Choi, Woo Seok ; Elkholy, Ahmed ; Kenney, Jack ; Hanumolu, Pavan Kumar. / A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-4
@inproceedings{c061f924e0c2466facb1d84730ef7e71,
title = "A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR",
abstract = "A sub-baud-rate CDR that can recover clock and data using only a quarter-rate clock is presented. Four data bits are recovered in each clock cycle using eight samplers and a current integrator. Four of the eight samplers used for data recovery are re-used for phase detection. Fabricated in a 65nm CMOS process and operating with 11dB channel loss, the prototype CDR recovers 15.2Gb/s data using a 3.8GHz clock and achieves BER < 10-12, > 10MHz JTOL corner, 548fsrms recovered clock jitter, and 1.9pJ/bit energy efficiency.",
keywords = "2x oversampling, baud-rate, Clock and data recovery (CDR), current integrator, sub-baud-rate",
author = "Dongwook Kim and Choi, {Woo Seok} and Ahmed Elkholy and Jack Kenney and Hanumolu, {Pavan Kumar}",
year = "2018",
month = "5",
day = "9",
doi = "10.1109/CICC.2018.8357078",
language = "English (US)",
pages = "1--4",
booktitle = "2018 IEEE Custom Integrated Circuits Conference, CICC 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

TY - GEN

T1 - A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR

AU - Kim, Dongwook

AU - Choi, Woo Seok

AU - Elkholy, Ahmed

AU - Kenney, Jack

AU - Hanumolu, Pavan Kumar

PY - 2018/5/9

Y1 - 2018/5/9

N2 - A sub-baud-rate CDR that can recover clock and data using only a quarter-rate clock is presented. Four data bits are recovered in each clock cycle using eight samplers and a current integrator. Four of the eight samplers used for data recovery are re-used for phase detection. Fabricated in a 65nm CMOS process and operating with 11dB channel loss, the prototype CDR recovers 15.2Gb/s data using a 3.8GHz clock and achieves BER < 10-12, > 10MHz JTOL corner, 548fsrms recovered clock jitter, and 1.9pJ/bit energy efficiency.

AB - A sub-baud-rate CDR that can recover clock and data using only a quarter-rate clock is presented. Four data bits are recovered in each clock cycle using eight samplers and a current integrator. Four of the eight samplers used for data recovery are re-used for phase detection. Fabricated in a 65nm CMOS process and operating with 11dB channel loss, the prototype CDR recovers 15.2Gb/s data using a 3.8GHz clock and achieves BER < 10-12, > 10MHz JTOL corner, 548fsrms recovered clock jitter, and 1.9pJ/bit energy efficiency.

KW - 2x oversampling

KW - baud-rate

KW - Clock and data recovery (CDR)

KW - current integrator

KW - sub-baud-rate

UR - http://www.scopus.com/inward/record.url?scp=85048076365&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85048076365&partnerID=8YFLogxK

U2 - 10.1109/CICC.2018.8357078

DO - 10.1109/CICC.2018.8357078

M3 - Conference contribution

AN - SCOPUS:85048076365

SP - 1

EP - 4

BT - 2018 IEEE Custom Integrated Circuits Conference, CICC 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -