@inproceedings{c061f924e0c2466facb1d84730ef7e71,
title = "A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR",
abstract = "A sub-baud-rate CDR that can recover clock and data using only a quarter-rate clock is presented. Four data bits are recovered in each clock cycle using eight samplers and a current integrator. Four of the eight samplers used for data recovery are re-used for phase detection. Fabricated in a 65nm CMOS process and operating with 11dB channel loss, the prototype CDR recovers 15.2Gb/s data using a 3.8GHz clock and achieves BER < 10-12, > 10MHz JTOL corner, 548fsrms recovered clock jitter, and 1.9pJ/bit energy efficiency.",
keywords = "2x oversampling, Clock and data recovery (CDR), baud-rate, current integrator, sub-baud-rate",
author = "Dongwook Kim and Choi, {Woo Seok} and Ahmed Elkholy and Jack Kenney and Hanumolu, {Pavan Kumar}",
note = "Funding Information: VI. ACKNOWLEDGMENT This work is in part supported by Semiconductor Research Corporation under Texas Analog Center of Excellence (Tx-ACE) Task 2712.009. Constructive feedback and insightful comments provided by Mostafa Ahmed and Da Wei of the University of Illinois are gratefully acknowledged. Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 ; Conference date: 08-04-2018 Through 11-04-2018",
year = "2018",
month = may,
day = "9",
doi = "10.1109/CICC.2018.8357078",
language = "English (US)",
series = "2018 IEEE Custom Integrated Circuits Conference, CICC 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--4",
booktitle = "2018 IEEE Custom Integrated Circuits Conference, CICC 2018",
address = "United States",
}