Abstract
This paper presents a sub-baud-rate clock and data recovery (CDR) circuit that can recover clock and data using only differential quarter-rate clocks. A combination of eight samplers and an integrator recover four data bits in each clock cycle. Four of the eight samplers are re-used for phase detection as well as for background calibration to improve the robustness of the CDR to process, voltage, and temperature variations. A continuous-time linear equalizer is used to compensate for inter-symbol interference up to 11 dB. The CDR prototype fabricated in a 65-nm CMOS recovers 15.2-Gb/s data using only differential 3.8-GHz clock and achieves bit error rate (BER) < 10 −12 , >10-MHz jitter tolerance (JTOL) corner, and 548 fs rms recovered clock jitter. The total power consumption is 29 mW, which translates to an energy efficiency of 1.9 pJ/bit.
| Original language | English (US) |
|---|---|
| Article number | 8599124 |
| Pages (from-to) | 685-695 |
| Number of pages | 11 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 54 |
| Issue number | 3 |
| DOIs | |
| State | Published - Mar 1 2019 |
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Keywords
- Baud-rate
- Clock and data recovery (CDR)
- Current integrator
- Digital CDR
- Phase detector (PD)
- Sub-baud-rate
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A 15-Gb/s sub-baud-rate digital CDR. / Kim, Dongwook; Choi, Woo Seok; Elkholy, Ahmed; Kenney, Jack; Hanumolu, Pavan Kumar.
In: IEEE Journal of Solid-State Circuits, Vol. 54, No. 3, 8599124, 01.03.2019, p. 685-695.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A 15-Gb/s sub-baud-rate digital CDR
AU - Kim, Dongwook
AU - Choi, Woo Seok
AU - Elkholy, Ahmed
AU - Kenney, Jack
AU - Hanumolu, Pavan Kumar
PY - 2019/3/1
Y1 - 2019/3/1
N2 - This paper presents a sub-baud-rate clock and data recovery (CDR) circuit that can recover clock and data using only differential quarter-rate clocks. A combination of eight samplers and an integrator recover four data bits in each clock cycle. Four of the eight samplers are re-used for phase detection as well as for background calibration to improve the robustness of the CDR to process, voltage, and temperature variations. A continuous-time linear equalizer is used to compensate for inter-symbol interference up to 11 dB. The CDR prototype fabricated in a 65-nm CMOS recovers 15.2-Gb/s data using only differential 3.8-GHz clock and achieves bit error rate (BER) < 10 −12 , >10-MHz jitter tolerance (JTOL) corner, and 548 fs rms recovered clock jitter. The total power consumption is 29 mW, which translates to an energy efficiency of 1.9 pJ/bit.
AB - This paper presents a sub-baud-rate clock and data recovery (CDR) circuit that can recover clock and data using only differential quarter-rate clocks. A combination of eight samplers and an integrator recover four data bits in each clock cycle. Four of the eight samplers are re-used for phase detection as well as for background calibration to improve the robustness of the CDR to process, voltage, and temperature variations. A continuous-time linear equalizer is used to compensate for inter-symbol interference up to 11 dB. The CDR prototype fabricated in a 65-nm CMOS recovers 15.2-Gb/s data using only differential 3.8-GHz clock and achieves bit error rate (BER) < 10 −12 , >10-MHz jitter tolerance (JTOL) corner, and 548 fs rms recovered clock jitter. The total power consumption is 29 mW, which translates to an energy efficiency of 1.9 pJ/bit.
KW - Baud-rate
KW - Clock and data recovery (CDR)
KW - Current integrator
KW - Digital CDR
KW - Phase detector (PD)
KW - Sub-baud-rate
UR - http://www.scopus.com/inward/record.url?scp=85062440565&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85062440565&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2018.2885540
DO - 10.1109/JSSC.2018.2885540
M3 - Article
VL - 54
SP - 685
EP - 695
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 3
M1 - 8599124
ER -