Abstract
This paper presents a sub-baud-rate clock and data recovery (CDR) circuit that can recover clock and data using only differential quarter-rate clocks. A combination of eight samplers and an integrator recover four data bits in each clock cycle. Four of the eight samplers are re-used for phase detection as well as for background calibration to improve the robustness of the CDR to process, voltage, and temperature variations. A continuous-time linear equalizer is used to compensate for inter-symbol interference up to 11 dB. The CDR prototype fabricated in a 65-nm CMOS recovers 15.2-Gb/s data using only differential 3.8-GHz clock and achieves bit error rate (BER) < 10 −12 , >10-MHz jitter tolerance (JTOL) corner, and 548 fs rms recovered clock jitter. The total power consumption is 29 mW, which translates to an energy efficiency of 1.9 pJ/bit.
Original language | English (US) |
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Article number | 8599124 |
Pages (from-to) | 685-695 |
Number of pages | 11 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 54 |
Issue number | 3 |
DOIs | |
State | Published - Mar 2019 |
Keywords
- Baud-rate
- Clock and data recovery (CDR)
- Current integrator
- Digital CDR
- Phase detector (PD)
- Sub-baud-rate
ASJC Scopus subject areas
- Electrical and Electronic Engineering