A 13b 315fs _rms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators

Time-to-digital converters (TDCs) were historically used in laser range-finding, automatic test equipment, and timing jitter measurements, but recent developments in the design of high-resolution TDCs have paved the way for mostly digital implementation of PLLs and ADCs. Among the state-of-the-art TDCs, a flash TDC is the simplest, but its resolution is technology-limited by the minimum gate delay [1]. A pipelined TDC overcomes the technology limitation, but the characteristics of the inter-stage time-residue amplifier are inherently nonlinear and are therefore difficult to control in a robust manner [2]. A MASH TDC can improve the resolution by leveraging oversampling and noise shaping, but extracting the quantization error in the time domain poses many challenges [3]. A single-loop phase-domain continuous-time (CT) ΔΣ in [4] is susceptible to analog circuit imperfections. Furthermore, sampling frequency, F _S, in all previous TDCs must be equal to the input carrier frequency, F _C, which limits the over-sampling ratio (OSR) to be at most F _C/(2xBandwidth). To overcome these drawbacks, we present a highly digital switched ring oscillator based TDC (SRO-TDC) that achieves noise shaping and is capable of operating at high OSRs. The prototype SRO-TDC achieves an integrated noise of 315fs _rms in a 1MHz signal bandwidth at an input carrier and sampling frequencies of 80MHz and 500MHz, respectively while consuming less than 2mW from a 1V supply. It is also capable of operating over a wide range of input carrier frequencies (0.6 to 750MHz) and sampling rates (50 to 750MS/s).