A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file

Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R Shanbhag, K. Soumyanath, Shekhar Y. Borkar

Research output: Contribution to journalArticle


This paper describes a 256-word × 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic technique for aggressive bitline active leakage reduction/tolerance to enable 16 bitcells/bitline, low-V t usage, and 50% keeper downsizing. Gate-source underdrive of - V cc on read-select transistors is established without additional supply/bias voltages or gate-oxide overstress. 8% faster read performance and 36% higher dc noise robustness is achieved compared to dual-V t bitline scheme optimized for high performance. Device-level measurements in the 130-nm technology show 703× bitline active leakage reduction, enabling continued V t scaling and robust bitline scalability beyond 130-nm generation. Sustained performance and robustness benefit of the pseudostatic technique against conventional dynamic bitline with keeper-upsizing is also presented.

Original languageEnglish (US)
Pages (from-to)624-632
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number5
StatePublished - May 1 2002


  • Bitline active leakage
  • DC noise robustness
  • Dual threshold voltage
  • Pseudostatic
  • Register files

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Krishnamurthy, R. K., Alvandpour, A., Balamurugan, G., Shanbhag, N. R., Soumyanath, K., & Borkar, S. Y. (2002). A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. IEEE Journal of Solid-State Circuits, 37(5), 624-632. https://doi.org/10.1109/4.997856