A 12b 10MS/s pipelined ADC using reference scaling

G. Ahn, P. K. Hanumolu, M. Kim, S. Takeuchi, T. Sugimoto, K. Hamashita, K. Takasuka, G. Ternes, U. Moon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 12b 10MS/s pipelined ADC using reference scaling achieves 62 dB SNDR and 72 dB SFDR for a IMHz input. The prototype IC fabricated in a 0.35μm CMOS process employs interstage amplifiers with 45dB open-loop gain and consumes 19mW from a 2.4V supply.

Original languageEnglish (US)
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages220-221
Number of pages2
StatePublished - Dec 1 2006
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: Jun 15 2006Jun 17 2006

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2006 Symposium on VLSI Circuits, VLSIC
CountryUnited States
CityHonolulu, HI
Period6/15/066/17/06

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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